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aspeed queue:

Browse source 
* Improve AST2700 co-processor models
 * Add vbootrom support to the ast2700fc multi-soc machine
 * Bump SDK version to v09.08 for the ast2700fc machine
 * Add 32 bits property for Aspeed GPIOs
 * Change ast2600-evb machine flash model to w25q512jv
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Merge tag 'pull-aspeed-20251022' of https://github.com/legoater/qemu into staging

aspeed queue:

* Improve AST2700 co-processor models
* Add vbootrom support to the ast2700fc multi-soc machine
* Bump SDK version to v09.08 for the ast2700fc machine
* Add 32 bits property for Aspeed GPIOs
* Change ast2600-evb machine flash model to w25q512jv

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# gpg: Signature made Wed 22 Oct 2025 07:29:23 AM CDT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full]
# gpg:                 aka "Cédric Le Goater <clg@kaod.org>" [full]

* tag 'pull-aspeed-20251022' of https://github.com/legoater/qemu:
  hw/arm/aspeed: Remove ast2700fc self-aliasing
  hw/arm/aspeed: ast2600-evb: Use w25q512jv flash model
  tests/qtest: Add qtest for for ASPEED GPIO gpio-set property
  hw/gpio: Add property for ASPEED GPIO in 32 bits basis
  tests/functional/aarch64/ast2700fc: Add vbootrom test
  tests/functional/aarch64/ast2700fc: Move coprocessor image loading to common function
  tests/functional/aarch64/ast2700fc: Add eth2 network interface check in PCIe test
  tests/functional/aarch64/ast2700fc: Update test ASPEED SDK v09.08
  hw/arm/aspeed_ast27x0-fc: Add VBOOTROM support
  hw/arm/aspeed_ast27x0-fc: Map FMC0 flash contents into CA35 boot ROM
  hw/arm/ast27x0: Share single UART set across PSP, SSP, and TSP
  hw/arm/ast27x0: Share single SCU instance across PSP, SSP, and TSP
  hw/arm/ast27x0: Add SRAM link and alias mapping for TSP coprocessor
  hw/arm/ast27x0: Add SRAM link and alias mapping for SSP coprocessor
  hw/arm/aspeed_ast27x0-tsp: Add SDRAM region and fix naming and size to 512MB
  hw/arm/aspeed_ast27x0-ssp: Add SDRAM region and fix naming and size to 512MB

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-10-22 08:00:52 -05:00
commit 93bc983201
12 changed files with 333 additions and 121 deletions
Download patch file Download diff file Expand all files Collapse all files

4
hw/arm/aspeed.c
View file

@ -1592,8 +1592,8 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc,
amc->soc_name = "ast2600-a3";
amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
amc->fmc_model = "mx66u51235f";
amc->spi_model = "mx66u51235f";
amc->fmc_model = "w25q512jv";
amc->spi_model = "w25q512jv";
amc->num_cs = 1;
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
ASPEED_MAC3_ON;

56
hw/arm/aspeed_ast27x0-fc.c
View file

@ -35,6 +35,7 @@ struct Ast2700FCState {
MemoryRegion ca35_memory;
MemoryRegion ca35_dram;
MemoryRegion ca35_boot_rom;
MemoryRegion ssp_memory;
MemoryRegion tsp_memory;
@ -44,8 +45,6 @@ struct Ast2700FCState {
Aspeed27x0SoCState ca35;
Aspeed27x0CoprocessorState ssp;
Aspeed27x0CoprocessorState tsp;
bool mmio_exec;
};
#define AST2700FC_BMC_RAM_SIZE (1 * GiB)
@ -61,6 +60,10 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
Ast2700FCState *s = AST2700A1FC(machine);
AspeedSoCState *soc;
AspeedSoCClass *sc;
const char *bios_name = NULL;
BlockBackend *fmc0 = NULL;
DeviceState *dev = NULL;
uint64_t rom_size;
object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a1");
soc = ASPEED_SOC(&s->ca35);
@ -93,6 +96,10 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
AST2700FC_HW_STRAP2, &error_abort);
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART12, sc->uarts_base,
sc->uarts_num, serial_hd(0));
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base,
sc->uarts_num, serial_hd(1));
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base,
sc->uarts_num, serial_hd(2));
if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) {
return false;
}
@ -108,6 +115,18 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
ast2700fc_board_info.ram_size = machine->ram_size;
ast2700fc_board_info.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
dev = ssi_get_cs(soc->fmc.spi, 0);
fmc0 = dev ? m25p80_get_blk(dev) : NULL;
if (fmc0) {
rom_size = memory_region_size(&soc->spi_boot);
aspeed_install_boot_rom(soc, fmc0, &s->ca35_boot_rom, rom_size);
}
/* VBOOTROM */
bios_name = machine->firmware ?: VBOOTROM_FILE_NAME;
aspeed_load_vbootrom(soc, bios_name, errp);
arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info);
return true;
@ -115,9 +134,9 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
{
AspeedCoprocessorState *soc;
AspeedCoprocessorClass *sc;
Ast2700FCState *s = AST2700A1FC(machine);
AspeedSoCState *psp = ASPEED_SOC(&s->ca35);
s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
clock_set_hz(s->ssp_sysclk, 200000000ULL);
@ -130,10 +149,14 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
object_property_set_link(OBJECT(&s->ssp), "memory",
OBJECT(&s->ssp_memory), &error_abort);
soc = ASPEED_COPROCESSOR(&s->ssp);
sc = ASPEED_COPROCESSOR_GET_CLASS(soc);
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base,
sc->uarts_num, serial_hd(1));
object_property_set_link(OBJECT(&s->ssp), "uart",
OBJECT(&psp->uart[4]), &error_abort);
object_property_set_int(OBJECT(&s->ssp), "uart-dev", ASPEED_DEV_UART4,
&error_abort);
object_property_set_link(OBJECT(&s->ssp), "sram",
OBJECT(&psp->sram), &error_abort);
object_property_set_link(OBJECT(&s->ssp), "scu",
OBJECT(&psp->scu), &error_abort);
if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) {
return false;
}
@ -143,9 +166,9 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
{
AspeedCoprocessorState *soc;
AspeedCoprocessorClass *sc;
Ast2700FCState *s = AST2700A1FC(machine);
AspeedSoCState *psp = ASPEED_SOC(&s->ca35);
s->tsp_sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");
clock_set_hz(s->tsp_sysclk, 200000000ULL);
@ -158,10 +181,14 @@ static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
object_property_set_link(OBJECT(&s->tsp), "memory",
OBJECT(&s->tsp_memory), &error_abort);
soc = ASPEED_COPROCESSOR(&s->tsp);
sc = ASPEED_COPROCESSOR_GET_CLASS(soc);
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base,
sc->uarts_num, serial_hd(2));
object_property_set_link(OBJECT(&s->tsp), "uart",
OBJECT(&psp->uart[7]), &error_abort);
object_property_set_int(OBJECT(&s->tsp), "uart-dev", ASPEED_DEV_UART7,
&error_abort);
object_property_set_link(OBJECT(&s->tsp), "sram",
OBJECT(&psp->sram), &error_abort);
object_property_set_link(OBJECT(&s->tsp), "scu",
OBJECT(&psp->scu), &error_abort);
if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) {
return false;
}
@ -180,7 +207,6 @@ static void ast2700fc_class_init(ObjectClass *oc, const void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
mc->alias = "ast2700fc";
mc->desc = "ast2700 full core support";
mc->init = ast2700fc_init;
mc->no_floppy = 1;

69
hw/arm/aspeed_ast27x0-ssp.c
View file

@ -16,10 +16,11 @@
#include "hw/arm/aspeed_soc.h"
#include "hw/arm/aspeed_coprocessor.h"
#define AST2700_SSP_RAM_SIZE (32 * MiB)
#define AST2700_SSP_SDRAM_SIZE (512 * MiB)
static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
[ASPEED_DEV_SRAM] = 0x00000000,
[ASPEED_DEV_SDRAM] = 0x00000000,
[ASPEED_DEV_SRAM] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
@ -132,17 +133,9 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj)
{
Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_COPROCESSOR(obj);
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(obj);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
int i;
object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
for (i = 0; i < sc->uarts_num; i++) {
object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
}
object_initialize_child(obj, "intc0", &a->intc[0],
TYPE_ASPEED_2700SSP_INTC);
@ -165,8 +158,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev_soc);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
DeviceState *armv7m;
g_autofree char *sram_name = NULL;
int uart;
g_autofree char *sdram_name = NULL;
int i;
if (!clock_has_source(s->sysclk)) {
@ -184,23 +176,29 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
OBJECT(s->memory), &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
sram_name = g_strdup_printf("aspeed.dram.%d",
CPU(a->armv7m.cpu)->cpu_index);
if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name,
AST2700_SSP_RAM_SIZE, errp)) {
/* SDRAM */
sdram_name = g_strdup_printf("aspeed.sdram.%d",
CPU(a->armv7m.cpu)->cpu_index);
if (!memory_region_init_ram(&s->sdram, OBJECT(s), sdram_name,
AST2700_SSP_SDRAM_SIZE, errp)) {
return;
}
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM],
&s->sram);
sc->memmap[ASPEED_DEV_SDRAM],
&s->sdram);
/* SRAM */
memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias",
s->sram, 0, memory_region_size(s->sram));
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
&s->sram_alias);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
sc->memmap[ASPEED_DEV_SCU]);
memory_region_init_alias(&s->scu_alias, OBJECT(s), "scu.alias",
&s->scu->iomem, 0,
memory_region_size(&s->scu->iomem));
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
&s->scu_alias);
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
@ -239,15 +237,19 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
}
/* UART */
for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
sc->memmap[uart], errp)) {
return;
}
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
aspeed_soc_ast27x0ssp_get_irq(s, uart));
}
memory_region_init_alias(&s->uart_alias, OBJECT(s), "uart.alias",
&s->uart->serial.io, 0,
memory_region_size(&s->uart->serial.io));
memory_region_add_subregion(s->memory, sc->memmap[s->uart_dev],
&s->uart_alias);
/*
* Redirect the UART interrupt to the NVIC, replacing the default routing
* to the PSP's GIC.
*/
sysbus_connect_irq(SYS_BUS_DEVICE(s->uart), 0,
aspeed_soc_ast27x0ssp_get_irq(s, s->uart_dev));
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),
"aspeed.timerctrl",
@ -278,9 +280,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
dc->realize = aspeed_soc_ast27x0ssp_realize;
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2700_A1_SILICON_REV;
sc->uarts_num = 13;
sc->uarts_base = ASPEED_DEV_UART0;
sc->irqmap = aspeed_soc_ast27x0ssp_irqmap;
sc->memmap = aspeed_soc_ast27x0ssp_memmap;
}

69
hw/arm/aspeed_ast27x0-tsp.c
View file

@ -16,10 +16,11 @@
#include "hw/arm/aspeed_soc.h"
#include "hw/arm/aspeed_coprocessor.h"
#define AST2700_TSP_RAM_SIZE (32 * MiB)
#define AST2700_TSP_SDRAM_SIZE (512 * MiB)
static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
[ASPEED_DEV_SRAM] = 0x00000000,
[ASPEED_DEV_SDRAM] = 0x00000000,
[ASPEED_DEV_SRAM] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
@ -132,17 +133,9 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj)
{
Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_COPROCESSOR(obj);
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(obj);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
int i;
object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
for (i = 0; i < sc->uarts_num; i++) {
object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
}
object_initialize_child(obj, "intc0", &a->intc[0],
TYPE_ASPEED_2700TSP_INTC);
@ -165,8 +158,7 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev_soc);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
DeviceState *armv7m;
g_autofree char *sram_name = NULL;
int uart;
g_autofree char *sdram_name = NULL;
int i;
if (!clock_has_source(s->sysclk)) {
@ -184,23 +176,29 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
OBJECT(s->memory), &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
sram_name = g_strdup_printf("aspeed.dram.%d",
CPU(a->armv7m.cpu)->cpu_index);
if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name,
AST2700_TSP_RAM_SIZE, errp)) {
/* SDRAM */
sdram_name = g_strdup_printf("aspeed.sdram.%d",
CPU(a->armv7m.cpu)->cpu_index);
if (!memory_region_init_ram(&s->sdram, OBJECT(s), sdram_name,
AST2700_TSP_SDRAM_SIZE, errp)) {
return;
}
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM],
&s->sram);
sc->memmap[ASPEED_DEV_SDRAM],
&s->sdram);
/* SRAM */
memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias",
s->sram, 0, memory_region_size(s->sram));
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
&s->sram_alias);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
}
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
sc->memmap[ASPEED_DEV_SCU]);
memory_region_init_alias(&s->scu_alias, OBJECT(s), "scu.alias",
&s->scu->iomem, 0,
memory_region_size(&s->scu->iomem));
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
&s->scu_alias);
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
@ -239,15 +237,19 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
}
/* UART */
for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
sc->memmap[uart], errp)) {
return;
}
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
aspeed_soc_ast27x0tsp_get_irq(s, uart));
}
memory_region_init_alias(&s->uart_alias, OBJECT(s), "uart.alias",
&s->uart->serial.io, 0,
memory_region_size(&s->uart->serial.io));
memory_region_add_subregion(s->memory, sc->memmap[s->uart_dev],
&s->uart_alias);
/*
* Redirect the UART interrupt to the NVIC, replacing the default routing
* to the PSP's GIC.
*/
sysbus_connect_irq(SYS_BUS_DEVICE(s->uart), 0,
aspeed_soc_ast27x0tsp_get_irq(s, s->uart_dev));
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),
"aspeed.timerctrl",
@ -278,9 +280,6 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
dc->realize = aspeed_soc_ast27x0tsp_realize;
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2700_A1_SILICON_REV;
sc->uarts_num = 13;
sc->uarts_base = ASPEED_DEV_UART0;
sc->irqmap = aspeed_soc_ast27x0tsp_irqmap;
sc->memmap = aspeed_soc_ast27x0tsp_memmap;
}

7
hw/arm/aspeed_coprocessor_common.c
View file

@ -25,6 +25,13 @@ static void aspeed_coprocessor_realize(DeviceState *dev, Error **errp)
static const Property aspeed_coprocessor_properties[] = {
DEFINE_PROP_LINK("memory", AspeedCoprocessorState, memory,
TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_LINK("sram", AspeedCoprocessorState, sram, TYPE_MEMORY_REGION,
MemoryRegion *),
DEFINE_PROP_LINK("scu", AspeedCoprocessorState, scu, TYPE_ASPEED_SCU,
AspeedSCUState *),
DEFINE_PROP_LINK("uart", AspeedCoprocessorState, uart, TYPE_SERIAL_MM,
SerialMM *),
DEFINE_PROP_INT32("uart-dev", AspeedCoprocessorState, uart_dev, 0),
};
static void aspeed_coprocessor_class_init(ObjectClass *oc, const void *data)

57
hw/gpio/aspeed_gpio.c
View file

@ -1308,6 +1308,57 @@ static void aspeed_gpio_2700_write(void *opaque, hwaddr offset,
}
/* Setup functions */
static void aspeed_gpio_set_set(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
{
uint32_t set_val = 0;
AspeedGPIOState *s = ASPEED_GPIO(obj);
AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
int set_idx = 0;
if (!visit_type_uint32(v, name, &set_val, errp)) {
return;
}
if (sscanf(name, "gpio-set[%d]", &set_idx) != 1) {
error_setg(errp, "%s: error reading %s", __func__, name);
return;
}
if (set_idx >= agc->nr_gpio_sets || set_idx < 0) {
error_setg(errp, "%s: invalid set_idx %s", __func__, name);
return;
}
aspeed_gpio_update(s, &s->sets[set_idx], set_val,
~s->sets[set_idx].direction);
}
static void aspeed_gpio_get_set(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
{
uint32_t set_val = 0;
AspeedGPIOState *s = ASPEED_GPIO(obj);
AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
int set_idx = 0;
if (sscanf(name, "gpio-set[%d]", &set_idx) != 1) {
error_setg(errp, "%s: error reading %s", __func__, name);
return;
}
if (set_idx >= agc->nr_gpio_sets || set_idx < 0) {
error_setg(errp, "%s: invalid set_idx %s", __func__, name);
return;
}
set_val = s->sets[set_idx].data_value;
visit_type_uint32(v, name, &set_val, errp);
}
/****************** Setup functions ******************/
static const GPIOSetProperties ast2400_set_props[ASPEED_GPIO_MAX_NR_SETS] = {
[0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} },
[1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} },
@ -1435,6 +1486,12 @@ static void aspeed_gpio_init(Object *obj)
g_free(name);
}
}
for (int i = 0; i < agc->nr_gpio_sets; i++) {
char *name = g_strdup_printf("gpio-set[%d]", i);
object_property_add(obj, name, "uint32", aspeed_gpio_get_set,
aspeed_gpio_set_set, NULL, NULL);
}
}
static const VMStateDescription vmstate_gpio_regs = {

14
include/hw/arm/aspeed_coprocessor.h
View file

@ -16,13 +16,18 @@ struct AspeedCoprocessorState {
DeviceState parent;
MemoryRegion *memory;
MemoryRegion sram;
MemoryRegion sdram;
MemoryRegion *sram;
MemoryRegion sram_alias;
MemoryRegion uart_alias;
MemoryRegion scu_alias;
Clock *sysclk;
AspeedSCUState scu;
AspeedSCUState *scu;
AspeedSCUState scuio;
AspeedTimerCtrlState timerctrl;
SerialMM uart[ASPEED_UARTS_NUM];
SerialMM *uart;
int uart_dev;
};
#define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor"
@ -34,11 +39,8 @@ struct AspeedCoprocessorClass {
/** valid_cpu_types: NULL terminated array of a single CPU type. */
const char * const *valid_cpu_types;
uint32_t silicon_rev;
const hwaddr *memmap;
const int *irqmap;
int uarts_base;
int uarts_num;
};
struct Aspeed27x0CoprocessorState {

1
include/qobject/qdict.h
View file

@ -57,6 +57,7 @@ void qdict_put_str(QDict *qdict, const char *key, const char *value);
double qdict_get_double(const QDict *qdict, const char *key);
int64_t qdict_get_int(const QDict *qdict, const char *key);
uint64_t qdict_get_uint(const QDict *qdict, const char *key);
bool qdict_get_bool(const QDict *qdict, const char *key);
QList *qdict_get_qlist(const QDict *qdict, const char *key);
QDict *qdict_get_qdict(const QDict *qdict, const char *key);

13
qobject/qdict.c
View file

@ -209,6 +209,19 @@ int64_t qdict_get_int(const QDict *qdict, const char *key)
return qnum_get_int(qobject_to(QNum, qdict_get(qdict, key)));
}
/**
* qdict_get_uint(): Get an unsigned integer mapped by 'key'
*
* This function assumes that 'key' exists and it stores a
* QNum representable as uint.
*
* Return unsigned integer mapped by 'key'.
*/
uint64_t qdict_get_uint(const QDict *qdict, const char *key)
{
return qnum_get_uint(qobject_to(QNum, qdict_get(qdict, key)));
}
/**
* qdict_get_bool(): Get a bool mapped by 'key'
*

55
tests/functional/aarch64/test_aspeed_ast2700fc.py
View file

@ -36,9 +36,20 @@ class AST2x00MachineSDK(QemuSystemTest):
exec_command_and_wait_for_pattern(self, 'root', 'Password:')
exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~#')
ASSET_SDK_V906_AST2700 = Asset(
'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.06/ast2700-default-obmc.tar.gz',
'f1d53e0be8a404ecce3e105f72bc50fa4e090ad13160ffa91b10a6e0233a9dc6')
def load_ast2700fc_coprocessor(self, name):
load_elf_list = {
'ssp': self.scratch_file(name, 'zephyr-aspeed-ssp.elf'),
'tsp': self.scratch_file(name, 'zephyr-aspeed-tsp.elf')
}
for cpu_num, key in enumerate(load_elf_list, start=4):
file = load_elf_list[key]
self.vm.add_args('-device',
f'loader,file={file},cpu-num={cpu_num}')
ASSET_SDK_V908_AST2700 = Asset(
'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.08/ast2700-default-obmc.tar.gz',
'eac3dc409b7ea3cd4b03d4792d3cebd469792ad893cb51e1d15f0fc20bd1e2cd')
def do_ast2700_i2c_test(self):
exec_command_and_wait_for_pattern(self,
@ -60,13 +71,16 @@ class AST2x00MachineSDK(QemuSystemTest):
'lspci -s 0002:01:00.0',
'0002:01:00.0 Ethernet controller: '
'Intel Corporation 82574L Gigabit Network Connection')
exec_command_and_wait_for_pattern(self,
'ip addr show dev eth2',
'inet 10.0.2.15/24')
def do_ast2700fc_ssp_test(self):
self.vm.shutdown()
self.vm.set_console(console_index=1)
self.vm.launch()
exec_command_and_wait_for_pattern(self, '\012', 'ssp:~$')
exec_command_and_wait_for_pattern(self, '\012', 'ssp_tsp:~$')
exec_command_and_wait_for_pattern(self, 'version',
'Zephyr version 3.7.1')
exec_command_and_wait_for_pattern(self, 'md 72c02000 1',
@ -120,23 +134,21 @@ class AST2x00MachineSDK(QemuSystemTest):
self.vm.add_args('-device',
f'loader,addr=0x430000000,cpu-num={i}')
load_elf_list = {
'ssp': self.scratch_file(name, 'zephyr-aspeed-ssp.elf'),
'tsp': self.scratch_file(name, 'zephyr-aspeed-tsp.elf')
}
for cpu_num, key in enumerate(load_elf_list, start=4):
file = load_elf_list[key]
self.vm.add_args('-device',
f'loader,file={file},cpu-num={cpu_num}')
self.load_ast2700fc_coprocessor(name)
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
def test_aarch64_ast2700fc_sdk_v09_06(self):
self.set_machine('ast2700fc')
def start_ast2700fc_test_vbootrom(self, name):
self.vm.add_args('-bios', 'ast27x0_bootrom.bin')
self.load_ast2700fc_coprocessor(name)
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
self.archive_extract(self.ASSET_SDK_V906_AST2700)
def test_aarch64_ast2700fc_sdk_v09_08(self):
self.set_machine('ast2700fc')
self.require_netdev('user')
self.archive_extract(self.ASSET_SDK_V908_AST2700)
self.start_ast2700fc_test('ast2700-default')
self.verify_openbmc_boot_and_login('ast2700-default')
self.do_ast2700_i2c_test()
@ -144,5 +156,14 @@ class AST2x00MachineSDK(QemuSystemTest):
self.do_ast2700fc_ssp_test()
self.do_ast2700fc_tsp_test()
def test_aarch64_ast2700fc_sdk_vbootrom_v09_08(self):
self.set_machine('ast2700fc')
self.archive_extract(self.ASSET_SDK_V908_AST2700)
self.start_ast2700fc_test_vbootrom('ast2700-default')
self.verify_openbmc_boot_and_login('ast2700-default')
self.do_ast2700fc_ssp_test()
self.do_ast2700fc_tsp_test()
if __name__ == '__main__':
QemuSystemTest.main()

105
tests/qtest/aspeed_gpio-test.c
View file

@ -27,28 +27,115 @@
#include "qemu/timer.h"
#include "qobject/qdict.h"
#include "libqtest-single.h"
#include "qemu/typedefs.h"
#define AST2600_GPIO_BASE 0x1E780000
#define GPIO_ABCD_DATA_VALUE 0x000
#define GPIO_ABCD_DIRECTION 0x004
static uint32_t qtest_qom_get_uint32(QTestState *s, const char *path,
const char *property)
{
QDict *r;
uint32_t res;
r = qtest_qmp(s, "{ 'execute': 'qom-get', 'arguments': "
"{ 'path': %s, 'property': %s } }", path, property);
res = qdict_get_uint(r, "return");
qobject_unref(r);
return res;
}
static void qtest_qom_set_uint32(QTestState *s, const char *path,
const char *property, uint32_t value)
{
QDict *r;
r = qtest_qmp(s, "{ 'execute': 'qom-set', 'arguments': "
"{ 'path': %s, 'property': %s, 'value': %" PRIu32 " } }",
path, property, value);
qobject_unref(r);
}
static const char *resp_get_error(QDict *r, const char* error_key)
{
QDict *qdict;
g_assert(r);
qdict = qdict_get_qdict(r, "error");
if (qdict) {
return qdict_get_str(qdict, error_key);
}
return NULL;
}
static bool qtest_qom_check_error(QTestState *s, const char *path,
const char *property, const char *error_msg,
const char *error_msg_key)
{
QDict *r;
bool b;
r = qtest_qmp(s, "{ 'execute': 'qom-get', 'arguments': "
"{ 'path': %s, 'property': %s } }", path, property);
b = g_str_equal(resp_get_error(r, error_msg_key), error_msg);
qobject_unref(r);
return b;
}
static void test_set_colocated_pins(const void *data)
{
QTestState *s = (QTestState *)data;
const char path[] = "/machine/soc/gpio";
/*
* gpioV4-7 occupy bits within a single 32-bit value, so we want to make
* sure that modifying one doesn't affect the other.
*/
qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV4", true);
qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV5", false);
qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV6", true);
qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV7", false);
g_assert(qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV4"));
g_assert(!qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV5"));
g_assert(qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV6"));
g_assert(!qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV7"));
qtest_qom_set_bool(s, path, "gpioV4", true);
qtest_qom_set_bool(s, path, "gpioV5", false);
qtest_qom_set_bool(s, path, "gpioV6", true);
qtest_qom_set_bool(s, path, "gpioV7", false);
g_assert(qtest_qom_get_bool(s, path, "gpioV4"));
g_assert(!qtest_qom_get_bool(s, path, "gpioV5"));
g_assert(qtest_qom_get_bool(s, path, "gpioV6"));
g_assert(!qtest_qom_get_bool(s, path, "gpioV7"));
/*
* Testing the gpio-set[%d] properties, using individual gpio boolean
* properties to do cross check.
* We use gpioR4-7 for test, Setting them to be 0b1010.
*/
qtest_qom_set_uint32(s, path, "gpio-set[4]", 0x0);
g_assert(qtest_qom_get_uint32(s, path, "gpio-set[4]") == 0x0);
qtest_qom_set_uint32(s, path, "gpio-set[4]", 0xa000);
g_assert(qtest_qom_get_uint32(s, path, "gpio-set[4]") == 0xa000);
g_assert(!qtest_qom_get_bool(s, path, "gpioR4"));
g_assert(qtest_qom_get_bool(s, path, "gpioR5"));
g_assert(!qtest_qom_get_bool(s, path, "gpioR6"));
g_assert(qtest_qom_get_bool(s, path, "gpioR7"));
/*
* Testing the invalid indexing, the response info should contain following
* info:
* {key: "class", value: "GenericError"}
*
* For pins, it should follow "gpio%2[A-Z]%1d" or "gpio%3[18A-E]%1d" format.
*/
const char error_msg[] = "GenericError";
const char error_msg_key[] = "class";
g_assert(qtest_qom_check_error(s, path, "gpioR+1", error_msg,
error_msg_key));
g_assert(qtest_qom_check_error(s, path, "gpio-set[99]", error_msg,
error_msg_key));
g_assert(qtest_qom_check_error(s, path, "gpio-set[-3]", error_msg,
error_msg_key));
}
static void test_set_input_pins(const void *data)

4
tests/qtest/aspeed_smc-test.c
View file

@ -134,10 +134,10 @@ static void test_ast2600_evb(AspeedSMCTestData *data)
"-drive file=%s,format=raw,if=mtd",
data->tmp_path);
/* fmc cs0 with mx66u51235f flash */
/* fmc cs0 with w25q512jv flash */
data->flash_base = 0x20000000;
data->spi_base = 0x1E620000;
data->jedec_id = 0xc2253a;
data->jedec_id = 0xef4020;
data->cs = 0;
data->node = "/machine/soc/fmc/ssi.0/child[0]";
/* beyond 16MB */