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target/arm: Fix BLXNS helper store alignment checks

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This patch adds alignment checks in the store operations (when stacking the
return pc and psr) in the BLXNS instruction.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154
Signed-off-by: William Kosasih <kosasihwilliam4@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250703085604.154449-3-kosasihwilliam4@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
William Kosasih 2025-07-03 18:25:55 +09:30 • committed by Peter Maydell
parent fa8f6f25ea
commit 94b07a46d1
1 changed files with 5 additions and 2 deletions
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7
target/arm/tcg/m_helper.c
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@ -632,8 +632,11 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
}
/* Note that these stores can throw exceptions on MPU faults */
cpu_stl_data_ra(env, sp, nextinst, GETPC());
cpu_stl_data_ra(env, sp + 4, saved_psr, GETPC());
ARMMMUIdx mmu_idx = arm_mmu_idx(env);
MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN,
arm_to_core_mmu_idx(mmu_idx));
cpu_stl_mmu(env, sp, nextinst, oi, GETPC());
cpu_stl_mmu(env, sp + 4, saved_psr, oi, GETPC());
env->regs[13] = sp;
env->regs[14] = 0xfeffffff;