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target/arm: Add gcs record for BLR

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Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20251008215613.300150-57-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2025-10-08 14:55:56 -07:00 • committed by Peter Maydell
parent a664ba1fc6
commit 978bad65f8
1 changed files with 8 additions and 8 deletions
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16
target/arm/tcg/translate-a64.c
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@ -1782,15 +1782,15 @@ static bool trans_BR(DisasContext *s, arg_r *a)
static bool trans_BLR(DisasContext *s, arg_r *a)
{
TCGv_i64 dst = cpu_reg(s, a->rn);
TCGv_i64 lr = cpu_reg(s, 30);
if (dst == lr) {
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_mov_i64(tmp, dst);
dst = tmp;
TCGv_i64 link = tcg_temp_new_i64();
gen_pc_plus_diff(s, link, 4);
if (s->gcs_en) {
gen_add_gcs_record(s, link);
}
gen_pc_plus_diff(s, lr, curr_insn_len(s));
gen_a64_set_pc(s, dst);
gen_a64_set_pc(s, cpu_reg(s, a->rn));
tcg_gen_mov_i64(cpu_reg(s, 30), link);
set_btype_for_blr(s);
s->base.is_jmp = DISAS_JUMP;
return true;