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intel_iommu: Declare supported PASID size

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the PSS field of the extended capabilities stores the supported PASID
size minus 1. This commit adds support for 8bits PASIDs (limited by
MemTxAttrs::pid).

Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com>
Message-Id: <20250628180226.133285-6-clement.mathieu--drif@eviden.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
CLEMENT MATHIEU--DRIF 2025-06-28 18:04:03 +00:00 • committed by Michael S. Tsirkin
parent f8eee3452f
commit 9b3725eec5
2 changed files with 2 additions and 1 deletions
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2
hw/i386/intel_iommu.c
View file

@ -4590,7 +4590,7 @@ static void vtd_cap_init(IntelIOMMUState *s)
}
if (s->pasid) {
s->ecap |= VTD_ECAP_PASID;
s->ecap |= VTD_ECAP_PASID | VTD_ECAP_PSS;
}
}

1
hw/i386/intel_iommu_internal.h
View file

@ -192,6 +192,7 @@
#define VTD_ECAP_SC (1ULL << 7)
#define VTD_ECAP_MHMV (15ULL << 20)
#define VTD_ECAP_SRS (1ULL << 31)
#define VTD_ECAP_PSS (7ULL << 35) /* limit: MemTxAttrs::pid */
#define VTD_ECAP_PASID (1ULL << 40)
#define VTD_ECAP_SMTS (1ULL << 43)
#define VTD_ECAP_SLTS (1ULL << 46)