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target/hppa: Adjust mmu indexes to begin with 0

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This is a logical reversion of 2ad0450054, though
there have been additions to the set of mmu indexes
since then.  The impetus to that original patch,
"9-15 will use shorter assembler instructions when
run on a x86-64 host" is now handled generically.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-07-11 18:35:59 -06:00
parent 33ea495cd3
commit 9ea2880581
1 changed files with 14 additions and 14 deletions
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28
target/hppa/cpu.h
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@ -29,21 +29,21 @@
#include "qemu/interval-tree.h"
#include "hw/registerfields.h"
#define MMU_ABS_W_IDX 6
#define MMU_ABS_IDX 7
#define MMU_KERNEL_IDX 8
#define MMU_KERNEL_P_IDX 9
#define MMU_PL1_IDX 10
#define MMU_PL1_P_IDX 11
#define MMU_PL2_IDX 12
#define MMU_PL2_P_IDX 13
#define MMU_USER_IDX 14
#define MMU_USER_P_IDX 15
#define MMU_KERNEL_IDX 0
#define MMU_KERNEL_P_IDX 1
#define MMU_PL1_IDX 2
#define MMU_PL1_P_IDX 3
#define MMU_PL2_IDX 4
#define MMU_PL2_P_IDX 5
#define MMU_USER_IDX 6
#define MMU_USER_P_IDX 7
#define MMU_ABS_IDX 8
#define MMU_ABS_W_IDX 9
#define MMU_IDX_MMU_DISABLED(MIDX) ((MIDX) < MMU_KERNEL_IDX)
#define MMU_IDX_TO_PRIV(MIDX) (((MIDX) - MMU_KERNEL_IDX) / 2)
#define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1)
#define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX)
#define MMU_IDX_MMU_DISABLED(MIDX) ((MIDX) >= MMU_ABS_IDX)
#define MMU_IDX_TO_PRIV(MIDX) ((MIDX) / 2)
#define MMU_IDX_TO_P(MIDX) ((MIDX) & 1)
#define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P))
#define PRIV_KERNEL 0
#define PRIV_USER 3