fridtjof/qemu-cr16
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

arm/cpu: Add sysreg definitions in cpu-sysregs.h

Browse source 
This new header contains macros that define aarch64 registers.
In a subsequent patch, this will be replaced by a more exhaustive
version that will be generated from linux arch/arm64/tools/sysreg
file. Those macros are sufficient to migrate the storage of those
ID regs from named fields in isar struct to an array cell.

[CH: reworked to use different structures]
[CH: moved accessors from the patches first using them to here,
     dropped interaction with writable registers, which will happen
     later]
[CH: use DEF magic suggested by rth]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20250617153931.1330449-2-cohuck@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Eric Auger 2025-07-01 15:08:26 +01:00 • committed by Peter Maydell
parent 9a3bf0e0ab
commit a2e3508ac0
4 changed files with 149 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

42
target/arm/cpu-sysregs.h Normal file
View file

@ -0,0 +1,42 @@
/*
* Definitions for Arm ID system registers
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef ARM_CPU_SYSREGS_H
#define ARM_CPU_SYSREGS_H
/*
* Following is similar to the coprocessor regs encodings, but with an argument
* ordering that matches the ARM ARM. We also reuse the various CP_REG_ defines
* that actually are the same as the equivalent KVM_REG_ values.
*/
#define ENCODE_ID_REG(op0, op1, crn, crm, op2) \
(((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) NAME##_IDX,
typedef enum ARMIDRegisterIdx {
#include "cpu-sysregs.h.inc"
NUM_ID_IDX,
} ARMIDRegisterIdx;
#undef DEF
#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \
SYS_##NAME = ENCODE_ID_REG(OP0, OP1, CRN, CRM, OP2),
typedef enum ARMSysRegs {
#include "cpu-sysregs.h.inc"
} ARMSysRegs;
#undef DEF
extern const uint32_t id_register_sysreg[NUM_ID_IDX];
int get_sysreg_idx(ARMSysRegs sysreg);
#endif /* ARM_CPU_SYSREGS_H */

36
target/arm/cpu-sysregs.h.inc Normal file
View file

@ -0,0 +1,36 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)
DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)
DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)
DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)
DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2)
DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0)
DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1)
DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)
DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3)
DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0)
DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1)
DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2)
DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4)
DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5)
DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6)
DEF(ID_MMFR3_EL1, 3, 0, 0, 1, 7)
DEF(ID_ISAR0_EL1, 3, 0, 0, 2, 0)
DEF(ID_ISAR1_EL1, 3, 0, 0, 2, 1)
DEF(ID_ISAR2_EL1, 3, 0, 0, 2, 2)
DEF(ID_ISAR3_EL1, 3, 0, 0, 2, 3)
DEF(ID_ISAR4_EL1, 3, 0, 0, 2, 4)
DEF(ID_ISAR5_EL1, 3, 0, 0, 2, 5)
DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6)
DEF(ID_ISAR6_EL1, 3, 0, 0, 2, 7)
DEF(MVFR0_EL1, 3, 0, 0, 3, 0)
DEF(MVFR1_EL1, 3, 0, 0, 3, 1)
DEF(MVFR2_EL1, 3, 0, 0, 3, 2)
DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4)
DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5)
DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6)
DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4)
DEF(CTR_EL0, 3, 3, 0, 0, 1)

49
target/arm/cpu.h
View file

@ -32,6 +32,7 @@
#include "qapi/qapi-types-common.h"
#include "target/arm/multiprocessing.h"
#include "target/arm/gtimer.h"
#include "target/arm/cpu-sysregs.h"
#define EXCP_UDEF 1 /* undefined instruction */
#define EXCP_SWI 2 /* software interrupt */
@ -834,6 +835,53 @@ typedef struct {
uint32_t map, init, supported;
} ARMVQMap;
/* REG is ID_XXX */
#define FIELD_DP64_IDREG(ISAR, REG, FIELD, VALUE) \
({ \
ARMISARegisters *i_ = (ISAR); \
uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \
regval = FIELD_DP64(regval, REG, FIELD, VALUE); \
i_->idregs[REG ## _EL1_IDX] = regval; \
})
#define FIELD_DP32_IDREG(ISAR, REG, FIELD, VALUE) \
({ \
ARMISARegisters *i_ = (ISAR); \
uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \
regval = FIELD_DP32(regval, REG, FIELD, VALUE); \
i_->idregs[REG ## _EL1_IDX] = regval; \
})
#define FIELD_EX64_IDREG(ISAR, REG, FIELD) \
({ \
const ARMISARegisters *i_ = (ISAR); \
FIELD_EX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
})
#define FIELD_EX32_IDREG(ISAR, REG, FIELD) \
({ \
const ARMISARegisters *i_ = (ISAR); \
FIELD_EX32(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
})
#define FIELD_SEX64_IDREG(ISAR, REG, FIELD) \
({ \
const ARMISARegisters *i_ = (ISAR); \
FIELD_SEX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
})
#define SET_IDREG(ISAR, REG, VALUE) \
({ \
ARMISARegisters *i_ = (ISAR); \
i_->idregs[REG ## _EL1_IDX] = VALUE; \
})
#define GET_IDREG(ISAR, REG) \
({ \
const ARMISARegisters *i_ = (ISAR); \
i_->idregs[REG ## _EL1_IDX]; \
})
/**
* ARMCPU:
* @env: #CPUARMState
@ -1040,6 +1088,7 @@ struct ArchCPU {
uint64_t id_aa64zfr0;
uint64_t id_aa64smfr0;
uint64_t reset_pmcr_el0;
uint64_t idregs[NUM_ID_IDX];
} isar;
uint64_t midr;
uint32_t revidr;

22
target/arm/cpu64.c
View file

@ -36,6 +36,28 @@
#include "cpu-features.h"
#include "cpregs.h"
/* convert between <register>_IDX and SYS_<register> */
#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \
[NAME##_IDX] = SYS_##NAME,
const uint32_t id_register_sysreg[NUM_ID_IDX] = {
#include "cpu-sysregs.h.inc"
};
#undef DEF
#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \
case SYS_##NAME: return NAME##_IDX;
int get_sysreg_idx(ARMSysRegs sysreg)
{
switch (sysreg) {
#include "cpu-sysregs.h.inc"
}
g_assert_not_reached();
}
#undef DEF
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
{
/*