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hw/dma/zynq-devcfg: Fix register memory

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Registers are always 32 bit aligned. R_MAX is not the maximum
register address, it is the maximum register number. The memory
size can be determined by 4 * R_MAX.

Currently every register with an offset bigger than 0x40 will be
ignored, because the memory size is set wrong. This effects the
MCTRL register and makes it useless. This commit restores the
correct behaviour.

Cc: qemu-stable@nongnu.org
Fixes: 034c2e6902 ("dma: Add Xilinx Zynq devcfg device model")
Signed-off-by: YannickV <Y.Vossen@beckhoff.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251111102836.212535-9-corvin.koehne@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Yannick Voßen 2025-11-11 11:28:29 +01:00 • committed by Philippe Mathieu-Daudé
parent 40260d3ea6
commit a344e22917
1 changed files with 1 additions and 1 deletions
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2
hw/dma/xlnx-zynq-devcfg.c
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@ -372,7 +372,7 @@ static void xlnx_zynq_devcfg_init(Object *obj)
s->regs_info, s->regs,
&xlnx_zynq_devcfg_reg_ops,
XLNX_ZYNQ_DEVCFG_ERR_DEBUG,
XLNX_ZYNQ_DEVCFG_R_MAX);
XLNX_ZYNQ_DEVCFG_R_MAX * 4);
memory_region_add_subregion(&s->iomem,
A_CTRL,
&reg_array->mem);