diff --git a/target/cr16c/disas.c b/target/cr16c/disas.c
index 623564d1bf..1460411d09 100644
--- a/target/cr16c/disas.c
+++ b/target/cr16c/disas.c
@@ -139,10 +139,120 @@ output(mnemonic, format, ##__VA_ARGS__);                            \
 return true;                                                        \
 }
 
-/*static const char width[] = {
-    'x', 'B', 'W', 'x', 'D'
-};*/
+/*
+static const char* width[] = {
+    "x", "B", "W", "x", "D"
+};
 
-//INSN(MOV_imm, "MOV" width[a->width], "$0x%x, r%d", width[a->width], a->imm, a->rd)
-//INSN(MOV_reg, "MOV" width[a->width], "r%d, r%d", width[a->width], a->rs, a->rd)
-//INSN(MOVD_reg, "MOVD", "r%d, r%d", a->rs, a->rd)
+INSN(UNIMPLEMENTED, "")
+
+INSN(LOAD, "")
+INSN(LOAD_rrp, "")
+INSN(LOAD_abs, "")
+INSN(LOAD_ind_abs, "")
+//INSN(LOADD, "")
+INSN(STOR, "")
+INSN(STOR_rrp, "")
+INSN(STOR_rrp_imm, "")
+INSN(STOR_abs, "")
+INSN(STOR_ind_abs, "")
+INSN(STOR_abs_imm, "")
+INSN(STOR_abs_rrp_imm, "")
+//INSN(STORD, "")
+INSN(STOR_imm, "$0x%x, r%d", a->imm, a->ra)
+INSN(LOADM, "$0x%x", a->cnt)
+//INSN(LOADMP, "$0x%x", a->cnt)
+INSN(STORM, "$0x%x", a->cnt)
+//INSN(STORMP, "$0x%x", a->cnt)
+
+INSN(MOV_reg, "%s r%d, r%d", width[a->width], a->rs, a->rd)
+INSN(MOV_imm, "%s $0x%x, r%d", width[a->width], a->imm, a->rd)
+INSN(MOVD_reg, "r%dr%d, r%dr%d", a->rs + 1, a->rs, a->rd + 1, a->rd)
+INSN(MOVXB, "r%d, r%d", a->rs, a->rd)
+INSN(MOVZB, "r%d, r%d", a->rs, a->rd)
+INSN(MOVXW, "r%d, r%d", a->rs, a->rd)
+INSN(MOVZW, "r%d, r%d", a->rs, a->rd)
+
+INSN(ADD_imm, "$0x%x, r%d", a->imm, a->rd)
+INSN(ADD_reg, "r%d, r%d", a->rs, a->rd)
+INSN(ADDU_imm, "$0x%x, r%d", a->imm, a->rd)
+INSN(ADDU_reg, "r%d, r%d", a->rs, a->rd)
+//INSN(ADDC_imm, "")
+//INSN(ADDC_reg, "r%d, r%d", a->rs, a->rd)
+INSN(ADDD_imm, "$0x%x, r%dr%d", a->imm, a->rd + 1, a->rd)
+INSN(ADDD_rp, "r%dr%d, r%dr%d", a->rs + 1, a->rs, a->rd + 1, a->rd)
+
+INSN(MACQW, "")
+INSN(MACSW, "")
+INSN(MACUW, "")
+INSN(MUL_imm, "")
+INSN(MULB_reg, "r%d, r%d", a->rs, a->rd)
+INSN(MULW_reg, "r%d, r%d", a->rs, a->rd)
+INSN(MULSB_reg, "r%d, r%d", a->rs, a->rd)
+INSN(MULSW_reg, "r%d, r%d", a->rs, a->rd)
+INSN(MULUW_reg, "r%d, r%d", a->rs, a->rd)
+INSN(SUB_imm, "")
+INSN(SUB_reg, "r%d, r%d", a->rs, a->rd)
+INSN(SUBD_imm, "")
+INSN(SUBD_rp, "")
+//INSN(SUBC_imm, "")
+//INSN(SUBC_reg, "")
+
+INSN(CMP_imm, "")
+INSN(CMP_reg, "")
+//INSN(CMPD_imm, "")
+INSN(CMPD_reg, "")
+INSN(BR0, "") // BEQ0, BNE0
+
+INSN(AND_imm, "")
+INSN(AND_reg, "")
+INSN(ANDD_imm, "")
+INSN(ANDD_rp, "")
+INSN(OR_imm, "")
+INSN(OR_reg, "")
+INSN(ORD_imm, "")
+INSN(ORD_rp, "")
+INSN(XOR_imm, "")
+INSN(XOR_reg, "")
+INSN(XORD_imm, "")
+INSN(XORD_rp, "")
+INSN(SCOND, "")
+
+INSN(ASHU_imm_l, "")
+INSN(ASHU_imm_r, "")
+INSN(ASHU_reg, "")
+INSN(ASHUD_imm_l, "")
+INSN(ASHUD_imm_r, "")
+INSN(ASHUD_rp, "")
+INSN(LSH_imm_r, "")
+INSN(LSH_reg, "")
+INSN(LSHD_imm_r, "")
+INSN(LSHD_rp, "")
+
+// TODO
+//INSN(TBIT, "")
+INSN(SBIT_abs, "")
+INSN(CBIT_abs, "")
+
+// TODO
+INSN(LPR, "")
+INSN(LPRD, "")
+INSN(SPR, "")
+INSN(SPRD, "")
+
+INSN(BRCOND, "")
+INSN(BAL_ra, "")
+// INSN(BR, "") // BRCOND condition "ALWAYS"
+INSN(EXCP, "")
+INSN(JCOND, "")
+//INSN(JAL, "")
+//INSN(JUMP, "") // JCOND condition "ALWAYS"
+//INSN(JUSR, "")
+//INSN(RETX, "")
+INSN(push, "")
+INSN(pop, "")
+
+//INSN(CINV, "")
+//INSN(NOP, "")
+//INSN(WAIT, "")
+*/