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MIPS patches queue

Browse source 
- Implement CRC32[c] (Release 6) instructions
 - Convert Octeon LX instructions to decodetree
 - Restrict ITU to TCG
 - Fix ESP issue affecting WinNT (INACCESSIBLE_BOOT_DEVICE BSOD)
 - Add missing FDT dependency for some MicroBlaze machines
 - Remove execute bit on hppa-firmware blobs
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmh18qYACgkQ4+MsLN6t
 wN6BKBAAnGgPvk1/8Pi0SJG9Swr60JE6VodL+89xgVglopcYAxN0hpcpq+W2ywgK
 uaOWNzfsyZZY7Zst35nLJKZrRjV6pXqOPqxLNIsJ8GHiVOXPUQTJIkBjgLs1b9kc
 +tR85U/JKTExP16FXQWzbSTqCOYsVoNtm6boYVjzno8BGv2C2ymDNr7a8oN9FWsS
 It/+5SpxwosmYf7jdbCRAwP/TRTFDGtV1JTjaEuZ19qj024hcBDTQ4qdQu7iIXF9
 eI7a9trIoGGUF7644z+XkYbSd2dghKqOaPmKDDSnW+pva26NpoG2EI4C9pkcvfrh
 4hvpAiwNbZ7erChIi5vlZsw84fUCptMVaoZWk+mu3Rif440FM02OA51dgUN3DCMV
 jddW5CzRcYlKxU//uMVdnmIY7T+KSEJJXUKOXa6vh623PdD4I14H9vrcP5t6lavE
 2G16+OJHMB0pQkDFgwiz4f1nglIxO4ujMP0Ow5wRDarCCI/4BWkMDAuWWAv05tXH
 zKsfHi5RSL2UtbNr0yd1e6Ph9ofm99RYOMGl0G8vyWbR4hVIAhfF8+qq0EfH9JCk
 t7vIigoU5FbP4JNaxJoNIIigFpyedC2nUPHYkeM4A2e5xW5oC/KGsp4XzzyfmJ3Y
 wpWAYFyB/7qAk8MfeAH6DTJ5s1Sz7xY0K0CrjIPnhCoLpXURwpA=
 =bhsu
 -----END PGP SIGNATURE-----

Merge tag 'mips-20250715' of https://github.com/philmd/qemu into staging

MIPS patches queue

- Implement CRC32[c] (Release 6) instructions
- Convert Octeon LX instructions to decodetree
- Restrict ITU to TCG
- Fix ESP issue affecting WinNT (INACCESSIBLE_BOOT_DEVICE BSOD)
- Add missing FDT dependency for some MicroBlaze machines
- Remove execute bit on hppa-firmware blobs

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmh18qYACgkQ4+MsLN6t
# wN6BKBAAnGgPvk1/8Pi0SJG9Swr60JE6VodL+89xgVglopcYAxN0hpcpq+W2ywgK
# uaOWNzfsyZZY7Zst35nLJKZrRjV6pXqOPqxLNIsJ8GHiVOXPUQTJIkBjgLs1b9kc
# +tR85U/JKTExP16FXQWzbSTqCOYsVoNtm6boYVjzno8BGv2C2ymDNr7a8oN9FWsS
# It/+5SpxwosmYf7jdbCRAwP/TRTFDGtV1JTjaEuZ19qj024hcBDTQ4qdQu7iIXF9
# eI7a9trIoGGUF7644z+XkYbSd2dghKqOaPmKDDSnW+pva26NpoG2EI4C9pkcvfrh
# 4hvpAiwNbZ7erChIi5vlZsw84fUCptMVaoZWk+mu3Rif440FM02OA51dgUN3DCMV
# jddW5CzRcYlKxU//uMVdnmIY7T+KSEJJXUKOXa6vh623PdD4I14H9vrcP5t6lavE
# 2G16+OJHMB0pQkDFgwiz4f1nglIxO4ujMP0Ow5wRDarCCI/4BWkMDAuWWAv05tXH
# zKsfHi5RSL2UtbNr0yd1e6Ph9ofm99RYOMGl0G8vyWbR4hVIAhfF8+qq0EfH9JCk
# t7vIigoU5FbP4JNaxJoNIIigFpyedC2nUPHYkeM4A2e5xW5oC/KGsp4XzzyfmJ3Y
# wpWAYFyB/7qAk8MfeAH6DTJ5s1Sz7xY0K0CrjIPnhCoLpXURwpA=
# =bhsu
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 15 Jul 2025 02:18:14 EDT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'mips-20250715' of https://github.com/philmd/qemu:
  esp.c: only allow ESP commands permitted in the current asc_mode
  esp.c: add asc_mode property to indicate the current ESP mode
  esp.c: only call dma_memory_write function if transfer length is non-zero
  esp.c: only call dma_memory_read function if transfer length is non-zero
  esp.h: remove separate ESPState typedef
  esp.c: improve comment in esp_transfer_data()
  esp.c: only raise IRQ in esp_transfer_data() for CMD_SEL, CMD_SELATN and CMD_TI commands
  hw/microblaze: Add missing FDT dependency
  hw/intc/loongarch_extioi: Remove unnecessary 'qemu/typedefs.h' include
  hw/mips: Restrict ITU to TCG
  roms: re-remove execute bit from hppa-firmware*
  tests/tcg/mips: Add tests for MIPS CRC32[c] instructions
  target/mips: Have gen_[d]lsa() callers add 1 to shift amount argument
  target/mips: Convert Octeon LX instructions to decodetree
  target/mips: Extract generic gen_lx() helper
  target/mips: Extract gen_base_index_addr() helper
  target/mips: Add support for emulation of CRC32 instructions

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2025-07-16 07:06:14 -04:00
commit a56ac09f5c
34 changed files with 1447 additions and 86 deletions
Download patch file Download diff file Expand all files Collapse all files

1
hw/intc/loongarch_extioi_kvm.c
View file

@ -6,7 +6,6 @@
*/
#include "qemu/osdep.h"
#include "qemu/typedefs.h"
#include "hw/intc/loongarch_extioi.h"
#include "linux/kvm.h"
#include "qapi/error.h"

4
hw/microblaze/Kconfig
View file

@ -1,7 +1,7 @@
config PETALOGIX_S3ADSP1800
bool
default y
depends on MICROBLAZE
depends on MICROBLAZE && FDT
select PFLASH_CFI01
select XILINX
select XILINX_AXI
@ -11,7 +11,7 @@ config PETALOGIX_S3ADSP1800
config PETALOGIX_ML605
bool
default y
depends on MICROBLAZE
depends on MICROBLAZE && FDT
select PFLASH_CFI01
select SERIAL_MM
select SSI_M25P80

2
hw/mips/Kconfig
View file

@ -76,7 +76,7 @@ config LOONGSON3V
config MIPS_CPS
bool
select MIPS_ITU
select MIPS_ITU if TCG
config MIPS_BOSTON
bool

4
hw/mips/cps.c
View file

@ -24,7 +24,7 @@
#include "hw/mips/mips.h"
#include "hw/qdev-clock.h"
#include "hw/qdev-properties.h"
#include "system/kvm.h"
#include "system/tcg.h"
#include "system/reset.h"
qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
@ -59,7 +59,7 @@ static bool cpu_mips_itu_supported(CPUMIPSState *env)
{
bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env);
return is_mt && !kvm_enabled();
return is_mt && tcg_enabled();
}
static void mips_cps_realize(DeviceState *dev, Error **errp)

1
hw/misc/Kconfig
View file

@ -119,6 +119,7 @@ config STM32L4X5_RCC
config MIPS_ITU
bool
depends on TCG
config MPS2_FPGAIO
bool

94
hw/scsi/esp.c
View file

@ -275,6 +275,7 @@ static int esp_select(ESPState *s)
if (!s->current_dev) {
/* No such drive */
s->rregs[ESP_RSTAT] = 0;
s->asc_mode = ESP_ASC_MODE_DIS;
s->rregs[ESP_RINTR] = INTR_DC;
esp_raise_irq(s);
return -1;
@ -284,6 +285,7 @@ static int esp_select(ESPState *s)
* Note that we deliberately don't raise the IRQ here: this will be done
* either in esp_transfer_data() or esp_command_complete()
*/
s->asc_mode = ESP_ASC_MODE_INI;
return 0;
}
@ -308,6 +310,7 @@ static void do_command_phase(ESPState *s)
if (!current_lun) {
/* No such drive */
s->rregs[ESP_RSTAT] = 0;
s->asc_mode = ESP_ASC_MODE_DIS;
s->rregs[ESP_RINTR] = INTR_DC;
s->rregs[ESP_RSEQ] = SEQ_0;
esp_raise_irq(s);
@ -487,8 +490,10 @@ static void esp_do_dma(ESPState *s)
case STAT_MO:
if (s->dma_memory_read) {
len = MIN(len, fifo8_num_free(&s->cmdfifo));
s->dma_memory_read(s->dma_opaque, buf, len);
esp_set_tc(s, esp_get_tc(s) - len);
if (len) {
s->dma_memory_read(s->dma_opaque, buf, len);
esp_set_tc(s, esp_get_tc(s) - len);
}
} else {
len = esp_fifo_pop_buf(s, buf, fifo8_num_used(&s->fifo));
len = MIN(fifo8_num_free(&s->cmdfifo), len);
@ -541,9 +546,11 @@ static void esp_do_dma(ESPState *s)
trace_esp_do_dma(cmdlen, len);
if (s->dma_memory_read) {
len = MIN(len, fifo8_num_free(&s->cmdfifo));
s->dma_memory_read(s->dma_opaque, buf, len);
fifo8_push_all(&s->cmdfifo, buf, len);
esp_set_tc(s, esp_get_tc(s) - len);
if (len) {
s->dma_memory_read(s->dma_opaque, buf, len);
fifo8_push_all(&s->cmdfifo, buf, len);
esp_set_tc(s, esp_get_tc(s) - len);
}
} else {
len = esp_fifo_pop_buf(s, buf, fifo8_num_used(&s->fifo));
len = MIN(fifo8_num_free(&s->cmdfifo), len);
@ -572,8 +579,10 @@ static void esp_do_dma(ESPState *s)
switch (s->rregs[ESP_CMD]) {
case CMD_TI | CMD_DMA:
if (s->dma_memory_read) {
s->dma_memory_read(s->dma_opaque, s->async_buf, len);
esp_set_tc(s, esp_get_tc(s) - len);
if (len) {
s->dma_memory_read(s->dma_opaque, s->async_buf, len);
esp_set_tc(s, esp_get_tc(s) - len);
}
} else {
/* Copy FIFO data to device */
len = MIN(s->async_len, ESP_FIFO_SZ);
@ -625,7 +634,9 @@ static void esp_do_dma(ESPState *s)
switch (s->rregs[ESP_CMD]) {
case CMD_TI | CMD_DMA:
if (s->dma_memory_write) {
s->dma_memory_write(s->dma_opaque, s->async_buf, len);
if (len) {
s->dma_memory_write(s->dma_opaque, s->async_buf, len);
}
} else {
/* Copy device data to FIFO */
len = MIN(len, fifo8_num_free(&s->fifo));
@ -675,6 +686,7 @@ static void esp_do_dma(ESPState *s)
buf[0] = s->status;
if (s->dma_memory_write) {
/* Length already non-zero */
s->dma_memory_write(s->dma_opaque, buf, len);
} else {
esp_fifo_push_buf(s, buf, len);
@ -709,6 +721,7 @@ static void esp_do_dma(ESPState *s)
buf[0] = 0;
if (s->dma_memory_write) {
/* Length already non-zero */
s->dma_memory_write(s->dma_opaque, buf, len);
} else {
esp_fifo_push_buf(s, buf, len);
@ -1012,6 +1025,7 @@ void esp_transfer_data(SCSIRequest *req, uint32_t len)
*/
s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
s->rregs[ESP_RSEQ] = SEQ_CD;
esp_raise_irq(s);
break;
case CMD_SELATNS | CMD_DMA:
@ -1022,20 +1036,21 @@ void esp_transfer_data(SCSIRequest *req, uint32_t len)
*/
s->rregs[ESP_RINTR] |= INTR_BS;
s->rregs[ESP_RSEQ] = SEQ_MO;
esp_raise_irq(s);
break;
case CMD_TI | CMD_DMA:
case CMD_TI:
/*
* Bus service interrupt raised because of initial change to
* DATA phase
* If the final COMMAND phase data was transferred using a TI
* command, clear ESP_CMD to terminate the TI command and raise
* the completion interrupt
*/
s->rregs[ESP_CMD] = 0;
s->rregs[ESP_RINTR] |= INTR_BS;
esp_raise_irq(s);
break;
}
esp_raise_irq(s);
}
/*
@ -1090,6 +1105,7 @@ void esp_hard_reset(ESPState *s)
fifo8_reset(&s->cmdfifo);
s->dma = 0;
s->dma_cb = NULL;
s->asc_mode = ESP_ASC_MODE_DIS;
s->rregs[ESP_CFG1] = 7;
}
@ -1113,6 +1129,38 @@ static void parent_esp_reset(ESPState *s, int irq, int level)
}
}
static bool esp_cmd_is_valid(ESPState *s, uint8_t cmd)
{
uint8_t cmd_group = (cmd & CMD_GRP_MASK) >> 4;
/* Always allow misc commands */
if (cmd_group == CMD_GRP_MISC) {
return true;
}
switch (s->asc_mode) {
case ESP_ASC_MODE_DIS:
/* Disconnected mode: only allow disconnected commands */
if (cmd_group == CMD_GRP_DISC) {
return true;
}
break;
case ESP_ASC_MODE_INI:
/* Initiator mode: allow initiator commands */
if (cmd_group == CMD_GRP_INIT) {
return true;
}
break;
default:
g_assert_not_reached();
}
trace_esp_invalid_cmd(cmd, s->asc_mode);
return false;
}
static void esp_run_cmd(ESPState *s)
{
uint8_t cmd = s->rregs[ESP_CMD];
@ -1158,6 +1206,7 @@ static void esp_run_cmd(ESPState *s)
break;
case CMD_MSGACC:
trace_esp_mem_writeb_cmd_msgacc(cmd);
s->asc_mode = ESP_ASC_MODE_DIS;
s->rregs[ESP_RINTR] |= INTR_DC;
s->rregs[ESP_RSEQ] = 0;
s->rregs[ESP_RFLAGS] = 0;
@ -1268,6 +1317,11 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
break;
case ESP_CMD:
s->rregs[saddr] = val;
if (!esp_cmd_is_valid(s, s->rregs[saddr])) {
s->rregs[ESP_RSTAT] |= INTR_IL;
esp_raise_irq(s);
break;
}
esp_run_cmd(s);
break;
case ESP_WBUSID ... ESP_WSYNO:
@ -1325,6 +1379,14 @@ static bool esp_is_between_version_5_and_6(void *opaque, int version_id)
return version_id >= 5 && version_id <= 6;
}
static bool esp_is_version_8(void *opaque, int version_id)
{
ESPState *s = ESP(opaque);
version_id = MIN(version_id, s->mig_version_id);
return version_id >= 8;
}
int esp_pre_save(void *opaque)
{
ESPState *s = ESP(object_resolve_path_component(
@ -1356,13 +1418,18 @@ static int esp_post_load(void *opaque, int version_id)
}
}
if (version_id < 8) {
/* Assume initiator mode to allow all commands to continue */
s->asc_mode = ESP_ASC_MODE_INI;
}
s->mig_version_id = vmstate_esp.version_id;
return 0;
}
const VMStateDescription vmstate_esp = {
.name = "esp",
.version_id = 7,
.version_id = 8,
.minimum_version_id = 3,
.post_load = esp_post_load,
.fields = (const VMStateField[]) {
@ -1394,6 +1461,7 @@ const VMStateDescription vmstate_esp = {
esp_is_between_version_5_and_6),
VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6),
VMSTATE_BOOL(drq_state, ESPState),
VMSTATE_UINT8_TEST(asc_mode, ESPState, esp_is_version_8),
VMSTATE_END_OF_LIST()
},
};

1
hw/scsi/trace-events
View file

@ -198,6 +198,7 @@ esp_mem_writeb_cmd_ensel(uint32_t val) "Enable selection (0x%2.2x)"
esp_mem_writeb_cmd_dissel(uint32_t val) "Disable selection (0x%2.2x)"
esp_mem_writeb_cmd_ti(uint32_t val) "Transfer Information (0x%2.2x)"
esp_set_phase(const char *phase) "setting bus phase to %s"
esp_invalid_cmd(uint8_t cmd, uint8_t asc_mode) "command 0x%x asc_mode 0x%x"
# esp-pci.c
esp_pci_error_invalid_dma_direction(void) "invalid DMA transfer direction"

15
include/hw/scsi/esp.h
View file

@ -14,7 +14,11 @@ typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
#define ESP_FIFO_SZ 16
#define ESP_CMDFIFO_SZ 32
typedef struct ESPState ESPState;
enum ESPASCMode {
ESP_ASC_MODE_DIS = 0, /* Disconnected */
ESP_ASC_MODE_INI = 1, /* Initiator */
ESP_ASC_MODE_TGT = 2 /* Target */
};
#define TYPE_ESP "esp"
OBJECT_DECLARE_SIMPLE_TYPE(ESPState, ESP)
@ -40,6 +44,7 @@ struct ESPState {
uint8_t cmdfifo_cdb_offset;
uint8_t lun;
uint32_t do_cmd;
uint8_t asc_mode;
bool data_ready;
int dma_enabled;
@ -106,6 +111,13 @@ struct SysBusESPState {
#define CMD_DMA 0x80
#define CMD_CMD 0x7f
#define CMD_GRP_MASK 0x70
#define CMD_GRP_MISC 0x00
#define CMD_GRP_INIT 0x01
#define CMD_GRP_TRGT 0x02
#define CMD_GRP_DISC 0x04
#define CMD_NOP 0x00
#define CMD_FLUSH 0x01
#define CMD_RESET 0x02
@ -140,6 +152,7 @@ struct SysBusESPState {
#define INTR_FC 0x08
#define INTR_BS 0x10
#define INTR_DC 0x20
#define INTR_IL 0x40
#define INTR_RST 0x80
#define SEQ_0 0x0

0
pc-bios/hppa-firmware.img Executable file → Normal file
View file

0
pc-bios/hppa-firmware64.img Executable file → Normal file
View file

10
target/mips/cpu-defs.c.inc
View file

@ -756,8 +756,9 @@ const mips_def_t mips_defs[] =
(1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
(1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
(1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_XNP) |
(1 << CP0C5_VP) | (1 << CP0C5_LLB) | (1 << CP0C5_MRP) |
(3 << CP0C5_GI),
.CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
(1 << CP0C5_FRE) | (1 << CP0C5_UFE),
.CP0_LLAddr_rw_bitmask = 0,
@ -796,8 +797,9 @@ const mips_def_t mips_defs[] =
(1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
(1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
(1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_XNP) |
(1 << CP0C5_VP) | (1 << CP0C5_LLB) | (1 << CP0C5_MRP) |
(3 << CP0C5_GI),
.CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
(1 << CP0C5_FRE) | (1 << CP0C5_UFE),
.CP0_LLAddr_rw_bitmask = 0,

2
target/mips/helper.h
View file

@ -21,6 +21,8 @@ DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)
#endif
DEF_HELPER_3(crc32, tl, tl, tl, i32)
DEF_HELPER_3(crc32c, tl, tl, tl, i32)
DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)
/* microMIPS functions */

1
target/mips/meson.build
View file

@ -7,6 +7,7 @@ mips_ss.add(files(
'gdbstub.c',
'msa.c',
))
mips_ss.add(zlib)
if have_system
subdir('system')

2
target/mips/tcg/micromips_translate.c.inc
View file

@ -1795,7 +1795,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
return;
case LSA:
check_insn(ctx, ISA_MIPS_R6);
gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2));
gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) + 1);
break;
case ALIGN:
check_insn(ctx, ISA_MIPS_R6);

4
target/mips/tcg/msa_translate.c
View file

@ -780,7 +780,7 @@ TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st);
static bool trans_LSA(DisasContext *ctx, arg_r *a)
{
return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
}
static bool trans_DLSA(DisasContext *ctx, arg_r *a)
@ -788,5 +788,5 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a)
if (TARGET_LONG_BITS != 64) {
return false;
}
return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
}

7
target/mips/tcg/nanomips_translate.c.inc
View file

@ -3626,12 +3626,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_p_lsx(ctx, rd, rs, rt);
break;
case NM_LSA:
/*
* In nanoMIPS, the shift field directly encodes the shift
* amount, meaning that the supported shift values are in
* the range 0 to 3 (instead of 1 to 4 in MIPSR6).
*/
gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) - 1);
gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2));
break;
case NM_EXTW:
gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));

8
target/mips/tcg/octeon.decode
View file

@ -1,6 +1,7 @@
# Octeon Architecture Module instruction set
#
# Copyright (C) 2022 Pavel Dovgalyuk
# Copyright (C) 2024 Philippe Mathieu-Daudé
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#
@ -39,3 +40,10 @@ CINS 011100 ..... ..... ..... ..... 11001 . @bitfield
POP 011100 rs:5 00000 rd:5 00000 10110 dw:1
SEQNE 011100 rs:5 rt:5 rd:5 00000 10101 ne:1
SEQNEI 011100 rs:5 rt:5 imm:s10 10111 ne:1
&lx base index rd
@lx ...... base:5 index:5 rd:5 ...... ..... &lx
LWX 011111 ..... ..... ..... 00000 001010 @lx
LHX 011111 ..... ..... ..... 00100 001010 @lx
LBUX 011111 ..... ..... ..... 00110 001010 @lx
LDX 011111 ..... ..... ..... 01000 001010 @lx

12
target/mips/tcg/octeon_translate.c
View file

@ -174,3 +174,15 @@ static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)
}
return true;
}
static bool trans_lx(DisasContext *ctx, arg_lx *a, MemOp mop)
{
gen_lx(ctx, a->rd, a->base, a->index, mop);
return true;
}
TRANS(LBUX, trans_lx, MO_UB);
TRANS(LHX, trans_lx, MO_SW);
TRANS(LWX, trans_lx, MO_SL);
TRANS(LDX, trans_lx, MO_UQ);

26
target/mips/tcg/op_helper.c
View file

@ -24,6 +24,8 @@
#include "exec/helper-proto.h"
#include "exec/memop.h"
#include "fpu_helper.h"
#include "qemu/crc32c.h"
#include <zlib.h>
static inline target_ulong bitswap(target_ulong v)
{
@ -142,6 +144,30 @@ target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,
return (int64_t)(int32_t)(uint32_t)tmp5;
}
/* these crc32 functions are based on target/loongarch/tcg/op_helper.c */
target_ulong helper_crc32(target_ulong val, target_ulong m, uint32_t sz)
{
uint8_t buf[8];
target_ulong mask = ((sz * 8) == 64) ?
(target_ulong) -1ULL :
((1ULL << (sz * 8)) - 1);
m &= mask;
stq_le_p(buf, m);
return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff);
}
target_ulong helper_crc32c(target_ulong val, target_ulong m, uint32_t sz)
{
uint8_t buf[8];
target_ulong mask = ((sz * 8) == 64) ?
(target_ulong) -1ULL :
((1ULL << (sz * 8)) - 1);
m &= mask;
stq_le_p(buf, m);
return (int32_t) (crc32c(val, buf, sz) ^ 0xffffffff);
}
void helper_fork(target_ulong arg1, target_ulong arg2)
{
/*

5
target/mips/tcg/rel6.decode
View file

@ -16,11 +16,16 @@
&r rs rt rd sa
&special3_crc rs rt c sz
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
@crc32 ...... rs:5 rt:5 ..... c:3 sz:2 ...... &special3_crc
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
CRC32 011111 ..... ..... 00000 ... .. 001111 @crc32
REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3)
REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2

16
target/mips/tcg/rel6_translate.c
View file

@ -23,7 +23,7 @@ bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a)
static bool trans_LSA(DisasContext *ctx, arg_r *a)
{
return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
}
static bool trans_DLSA(DisasContext *ctx, arg_r *a)
@ -31,5 +31,17 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a)
if (TARGET_LONG_BITS != 64) {
return false;
}
return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
}
static bool trans_CRC32(DisasContext *ctx, arg_special3_crc *a)
{
if (unlikely(!ctx->crcp)
|| unlikely((a->sz == 3) && (!(ctx->hflags & MIPS_HFLAG_64)))
|| unlikely((a->c >= 2))) {
gen_reserved_instruction(ctx);
return true;
}
gen_crc32(ctx, a->rt, a->rs, a->rt, a->sz, a->c);
return true;
}

102
target/mips/tcg/translate.c
View file

@ -1957,6 +1957,17 @@ void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset)
}
}
void gen_base_index_addr(DisasContext *ctx, TCGv addr, int base, int index)
{
if (base == 0) {
gen_load_gpr(addr, index);
} else if (index == 0) {
gen_load_gpr(addr, base);
} else {
gen_op_addr_add(ctx, addr, cpu_gpr[base], cpu_gpr[index]);
}
}
static target_ulong pc_relative_pc(DisasContext *ctx)
{
target_ulong pc = ctx->base.pc_next;
@ -2025,6 +2036,15 @@ static void gen_lxr(DisasContext *ctx, TCGv reg, TCGv addr,
tcg_gen_or_tl(reg, t0, t1);
}
void gen_lx(DisasContext *ctx, int rd, int base, int index, MemOp mop)
{
TCGv t0 = tcg_temp_new();
gen_base_index_addr(ctx, t0, base, index);
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | mop);
gen_store_gpr(t0, rd);
}
/* Load */
static void gen_ld(DisasContext *ctx, uint32_t opc,
int rt, int base, int offset)
@ -10546,13 +10566,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv t0 = tcg_temp_new();
if (base == 0) {
gen_load_gpr(t0, index);
} else if (index == 0) {
gen_load_gpr(t0, base);
} else {
gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
}
gen_base_index_addr(ctx, t0, base, index);
/*
* Don't do NOP if destination is zero: we must perform the actual
* memory access.
@ -11323,47 +11337,6 @@ enum {
/* MIPSDSP functions. */
/* Indexed load is not for DSP only */
static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
int rd, int base, int offset)
{
TCGv t0;
if (!(ctx->insn_flags & INSN_OCTEON)) {
check_dsp(ctx);
}
t0 = tcg_temp_new();
if (base == 0) {
gen_load_gpr(t0, offset);
} else if (offset == 0) {
gen_load_gpr(t0, base);
} else {
gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]);
}
switch (opc) {
case OPC_LBUX:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
gen_store_gpr(t0, rd);
break;
case OPC_LHX:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW);
gen_store_gpr(t0, rd);
break;
case OPC_LWX:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
gen_store_gpr(t0, rd);
break;
#if defined(TARGET_MIPS64)
case OPC_LDX:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t0, rd);
break;
#endif
}
}
static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
int ret, int v1, int v2)
{
@ -13449,6 +13422,29 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
}
}
void gen_crc32(DisasContext *ctx, int rd, int rs, int rt, int sz,
int crc32c)
{
TCGv t0;
TCGv t1;
TCGv_i32 tsz = tcg_constant_i32(1 << sz);
if (rd == 0) {
/* Treat as NOP. */
return;
}
t0 = tcg_temp_new();
t1 = tcg_temp_new();
gen_load_gpr(t0, rt);
gen_load_gpr(t1, rs);
if (crc32c) {
gen_helper_crc32c(cpu_gpr[rd], t0, t1, tsz);
} else {
gen_helper_crc32(cpu_gpr[rd], t0, t1, tsz);
}
}
static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
{
int rs, rt, rd, sa;
@ -13611,15 +13607,22 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_LX_DSP:
check_dsp(ctx);
op2 = MASK_LX(ctx->opcode);
switch (op2) {
#if defined(TARGET_MIPS64)
case OPC_LDX:
gen_lx(ctx, rd, rs, rt, MO_UQ);
break;
#endif
case OPC_LBUX:
gen_lx(ctx, rd, rs, rt, MO_UB);
break;
case OPC_LHX:
gen_lx(ctx, rd, rs, rt, MO_SW);
break;
case OPC_LWX:
gen_mips_lx(ctx, op2, rd, rs, rt);
gen_lx(ctx, rd, rs, rt, MO_SL);
break;
default: /* Invalid */
MIPS_INVAL("MASK LX");
@ -15095,6 +15098,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1;
ctx->gi = (env->CP0_Config5 >> CP0C5_GI) & 3;
ctx->crcp = (env->CP0_Config5 >> CP0C5_CRCP) & 1;
restore_cpu_state(env, ctx);
#ifdef CONFIG_USER_ONLY
ctx->mem_idx = MIPS_HFLAG_UM;

4
target/mips/tcg/translate.h
View file

@ -51,6 +51,7 @@ typedef struct DisasContext {
bool abs2008;
bool mi;
int gi;
bool crcp;
} DisasContext;
#define DISAS_STOP DISAS_TARGET_0
@ -153,6 +154,7 @@ void check_cp1_registers(DisasContext *ctx, int regs);
void check_cop1x(DisasContext *ctx);
void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
void gen_base_index_addr(DisasContext *ctx, TCGv addr, int base, int index);
void gen_move_low32(TCGv ret, TCGv_i64 arg);
void gen_move_high32(TCGv ret, TCGv_i64 arg);
void gen_load_gpr(TCGv t, int reg);
@ -167,6 +169,7 @@ void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
int get_fp_bit(int cc);
void gen_lx(DisasContext *ctx, int rd, int base, int index, MemOp mop);
void gen_ldxs(DisasContext *ctx, int base, int index, int rd);
void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp);
void gen_addiupc(DisasContext *ctx, int rx, int imm,
@ -181,6 +184,7 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel);
void gen_crc32(DisasContext *ctx, int rd, int rs, int rt, int sz, int crc32c);
extern TCGv cpu_gpr[32], cpu_PC;
#if defined(TARGET_MIPS64)

4
target/mips/tcg/translate_addr_const.c
View file

@ -26,7 +26,7 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
t1 = tcg_temp_new();
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
tcg_gen_shli_tl(t0, t0, sa + 1);
tcg_gen_shli_tl(t0, t0, sa);
tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
return true;
@ -47,7 +47,7 @@ bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
t1 = tcg_temp_new();
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
tcg_gen_shli_tl(t0, t0, sa + 1);
tcg_gen_shli_tl(t0, t0, sa);
tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
return true;
}

32
tests/tcg/mips/include/wrappers_mips64r6.h
View file

@ -23,6 +23,7 @@
#ifndef WRAPPERS_MIPS64R6_H
#define WRAPPERS_MIPS64R6_H
#include <string.h>
#define DO_MIPS64R6__RD__RS(suffix, mnemonic) \
static inline void do_mips64r6_##suffix(const void *input, \
@ -80,4 +81,35 @@ DO_MIPS64R6__RD__RS_RT(DMULU, dmulu)
DO_MIPS64R6__RD__RS_RT(DMUHU, dmuhu)
#define DO_MIPS64R6__RT__RS_RT(suffix, mnemonic) \
static inline void do_mips64r6_##suffix(const void *input1, \
const void *input2, \
void *output) \
{ \
if (strncmp(#mnemonic, "crc32", 5) == 0) \
__asm__ volatile ( \
".set crc\n\t" \
); \
\
__asm__ volatile ( \
"ld $t1, 0(%0)\n\t" \
"ld $t2, 0(%1)\n\t" \
#mnemonic " $t2, $t1, $t2\n\t" \
"sd $t2, 0(%2)\n\t" \
: \
: "r" (input1), "r" (input2), "r" (output) \
: "t0", "t1", "t2", "memory" \
); \
}
DO_MIPS64R6__RT__RS_RT(CRC32B, crc32b)
DO_MIPS64R6__RT__RS_RT(CRC32H, crc32h)
DO_MIPS64R6__RT__RS_RT(CRC32W, crc32w)
DO_MIPS64R6__RT__RS_RT(CRC32D, crc32d)
DO_MIPS64R6__RT__RS_RT(CRC32CB, crc32cb)
DO_MIPS64R6__RT__RS_RT(CRC32CH, crc32ch)
DO_MIPS64R6__RT__RS_RT(CRC32CW, crc32cw)
DO_MIPS64R6__RT__RS_RT(CRC32CD, crc32cd)
#endif

40
tests/tcg/mips/user/isa/mips64r6/crc/Makefile Normal file
View file

@ -0,0 +1,40 @@
#
# Test program for MIPS64R6 CRC32 instructions
#
# Copyright (C) 2025 Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
#
# SPDX-License-Identifier: GPL-2.0-or-later
#
ifndef PREFIX
$(error "PREFIX not set, please export GNU Toolchain install directory.")
endif
ifndef SYSROOT
$(error "SYSROOT not set, please export GNU Toolchain system root directory.")
endif
SIM = ../../../../../../../build/qemu-mips64
SIM_FLAGS = -L $(SYSROOT)
CC = $(PREFIX)/bin/mips64-r6-linux-gnu-gcc
TESTCASES = test_mips64r6_crc32b.tst
TESTCASES += test_mips64r6_crc32h.tst
TESTCASES += test_mips64r6_crc32w.tst
TESTCASES += test_mips64r6_crc32d.tst
TESTCASES += test_mips64r6_crc32cb.tst
TESTCASES += test_mips64r6_crc32ch.tst
TESTCASES += test_mips64r6_crc32cw.tst
TESTCASES += test_mips64r6_crc32cd.tst
all: $(TESTCASES)
@for case in $(TESTCASES); do \
echo $(SIM) $(SIM_FLAGS) ./$$case; \
$(SIM) $(SIM_FLAGS) ./$$case; \
echo $(RM) -rf ./$$case; \
$(RM) -rf ./$$case; \
done
%.tst: %.c
$(CC) $< -o $@

142
tests/tcg/mips/user/isa/mips64r6/crc/test_mips64r6_crc32b.c Normal file
View file

@ -0,0 +1,142 @@
/*
* Test program for MIPS64R6 instruction CRC32B
*
* Copyright (C) 2019 Wave Computing, Inc.
* Copyright (C) 2019 Aleksandar Markovic <amarkovic@wavecomp.com>
* Copyright (C) 2025 Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_mips64r6.h"
#include "../../../../include/test_inputs_64.h"
#include "../../../../include/test_utils_64.h"
#define TEST_COUNT_TOTAL (PATTERN_INPUTS_64_COUNT + RANDOM_INPUTS_64_COUNT)
int32_t main(void)
{
char *isa_ase_name = "mips64r6";
char *group_name = "CRC with reversed polynomial 0xEDB88320";
char *instruction_name = "CRC32B";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b64_result[TEST_COUNT_TOTAL];
uint64_t b64_expect[TEST_COUNT_TOTAL] = {
0x0000000000ffffffULL, /* 0 */
0x000000002d02ef8dULL,
0x000000001bab0fd1ULL,
0x0000000036561fa3ULL,
0xffffffffbf1caddaULL,
0xffffffff92e1bda8ULL,
0x00000000278c7949ULL,
0x000000000a71693bULL,
0x000000002dfd1072ULL, /* 8 */
0x0000000000000000ULL,
0x0000000036a9e05cULL,
0x000000001b54f02eULL,
0xffffffff921e4257ULL,
0xffffffffbfe35225ULL,
0x000000000a8e96c4ULL,
0x00000000277386b6ULL,
0x000000001bfe5a84ULL, /* 16 */
0x0000000036034af6ULL,
0x0000000000aaaaaaULL,
0x000000002d57bad8ULL,
0xffffffffa41d08a1ULL,
0xffffffff89e018d3ULL,
0x000000003c8ddc32ULL,
0x000000001170cc40ULL,
0x0000000036fcb509ULL, /* 24 */
0x000000001b01a57bULL,
0x000000002da84527ULL,
0x0000000000555555ULL,
0xffffffff891fe72cULL,
0xffffffffa4e2f75eULL,
0x00000000118f33bfULL,
0x000000003c7223cdULL,
0xffffffffbf2f9ee9ULL, /* 32 */
0xffffffff92d28e9bULL,
0xffffffffa47b6ec7ULL,
0xffffffff89867eb5ULL,
0x0000000000ccccccULL,
0x000000002d31dcbeULL,
0xffffffff985c185fULL,
0xffffffffb5a1082dULL,
0xffffffff922d7164ULL, /* 40 */
0xffffffffbfd06116ULL,
0xffffffff8979814aULL,
0xffffffffa4849138ULL,
0x000000002dce2341ULL,
0x0000000000333333ULL,
0xffffffffb55ef7d2ULL,
0xffffffff98a3e7a0ULL,
0x0000000027fdbe55ULL, /* 48 */
0x000000000a00ae27ULL,
0x000000003ca94e7bULL,
0x0000000011545e09ULL,
0xffffffff981eec70ULL,
0xffffffffb5e3fc02ULL,
0x00000000008e38e3ULL,
0x000000002d732891ULL,
0x000000000aff51d8ULL, /* 56 */
0x00000000270241aaULL,
0x0000000011aba1f6ULL,
0x000000003c56b184ULL,
0xffffffffb51c03fdULL,
0xffffffff98e1138fULL,
0x000000002d8cd76eULL,
0x000000000071c71cULL,
0x0000000000286255ULL, /* 64 */
0x00000000784a5a65ULL,
0xffffffff9bdd0d3bULL,
0xffffffffe7e61ce5ULL,
0x00000000782fabf7ULL,
0x00000000004d93c7ULL,
0xffffffffe3dac499ULL,
0xffffffff9fe1d547ULL,
0xffffffff9b4ca0e5ULL, /* 72 */
0xffffffffe32e98d5ULL,
0x0000000000b9cf8bULL,
0x000000007c82de55ULL,
0xffffffffe7904f52ULL,
0xffffffff9ff27762ULL,
0x000000007c65203cULL,
0x00000000005e31e2ULL,
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_CRC32B(b64_pattern + i, b64_pattern + j,
b64_result + (PATTERN_INPUTS_64_SHORT_COUNT * i + j));
}
}
for (i = 0; i < RANDOM_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_CRC32B(b64_random + i, b64_random + j,
b64_result + (((PATTERN_INPUTS_64_SHORT_COUNT) *
(PATTERN_INPUTS_64_SHORT_COUNT)) +
RANDOM_INPUTS_64_SHORT_COUNT * i + j));
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results_64(isa_ase_name, group_name, instruction_name,
TEST_COUNT_TOTAL, elapsed_time, b64_result,
b64_expect);
return ret;
}

142
tests/tcg/mips/user/isa/mips64r6/crc/test_mips64r6_crc32cb.c Normal file
View file

@ -0,0 +1,142 @@
/*
* Test program for MIPS64R6 instruction CRC32CB
*
* Copyright (C) 2019 Wave Computing, Inc.
* Copyright (C) 2019 Aleksandar Markovic <amarkovic@wavecomp.com>
* Copyright (C) 2025 Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_mips64r6.h"
#include "../../../../include/test_inputs_64.h"
#include "../../../../include/test_utils_64.h"
#define TEST_COUNT_TOTAL (PATTERN_INPUTS_64_COUNT + RANDOM_INPUTS_64_COUNT)
int32_t main(void)
{
char *isa_ase_name = "mips64r6";
char *group_name = "CRC with reversed polynomial 0x82F63B78";
char *instruction_name = "CRC32CB";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b64_result[TEST_COUNT_TOTAL];
uint64_t b64_expect[TEST_COUNT_TOTAL] = {
0x0000000000ffffffULL, /* 0 */
0xffffffffad7d5351ULL,
0x00000000647e6465ULL,
0xffffffffc9fcc8cbULL,
0x00000000237f7689ULL,
0xffffffff8efdda27ULL,
0xffffffff837defedULL,
0x000000002eff4343ULL,
0xffffffffad82acaeULL, /* 8 */
0x0000000000000000ULL,
0xffffffffc9033734ULL,
0x0000000064819b9aULL,
0xffffffff8e0225d8ULL,
0x0000000023808976ULL,
0x000000002e00bcbcULL,
0xffffffff83821012ULL,
0x00000000642b3130ULL, /* 16 */
0xffffffffc9a99d9eULL,
0x0000000000aaaaaaULL,
0xffffffffad280604ULL,
0x0000000047abb846ULL,
0xffffffffea2914e8ULL,
0xffffffffe7a92122ULL,
0x000000004a2b8d8cULL,
0xffffffffc9566261ULL, /* 24 */
0x0000000064d4cecfULL,
0xffffffffadd7f9fbULL,
0x0000000000555555ULL,
0xffffffffead6eb17ULL,
0x00000000475447b9ULL,
0x000000004ad47273ULL,
0xffffffffe756deddULL,
0x00000000234c45baULL, /* 32 */
0xffffffff8ecee914ULL,
0x0000000047cdde20ULL,
0xffffffffea4f728eULL,
0x0000000000ccccccULL,
0xffffffffad4e6062ULL,
0xffffffffa0ce55a8ULL,
0x000000000d4cf906ULL,
0xffffffff8e3116ebULL, /* 40 */
0x0000000023b3ba45ULL,
0xffffffffeab08d71ULL,
0x00000000473221dfULL,
0xffffffffadb19f9dULL,
0x0000000000333333ULL,
0x000000000db306f9ULL,
0xffffffffa031aa57ULL,
0xffffffff830c28f1ULL, /* 48 */
0x000000002e8e845fULL,
0xffffffffe78db36bULL,
0x000000004a0f1fc5ULL,
0xffffffffa08ca187ULL,
0x000000000d0e0d29ULL,
0x00000000008e38e3ULL,
0xffffffffad0c944dULL,
0x000000002e717ba0ULL, /* 56 */
0xffffffff83f3d70eULL,
0x000000004af0e03aULL,
0xffffffffe7724c94ULL,
0x000000000df1f2d6ULL,
0xffffffffa0735e78ULL,
0xffffffffadf36bb2ULL,
0x000000000071c71cULL,
0x0000000000286255ULL, /* 64 */
0xffffffffcbefd6b4ULL,
0xffffffffc334e94fULL,
0xffffffffac268ec5ULL,
0xffffffffcb8a2726ULL,
0x00000000004d93c7ULL,
0x000000000896ac3cULL,
0x000000006784cbb6ULL,
0xffffffffc3a54491ULL, /* 72 */
0x000000000862f070ULL,
0x0000000000b9cf8bULL,
0x000000006faba801ULL,
0xffffffffac50dd72ULL,
0x0000000067976993ULL,
0x000000006f4c5668ULL,
0x00000000005e31e2ULL,
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_CRC32CB(b64_pattern + i, b64_pattern + j,
b64_result + (PATTERN_INPUTS_64_SHORT_COUNT * i + j));
}
}
for (i = 0; i < RANDOM_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_CRC32CB(b64_random + i, b64_random + j,
b64_result + (((PATTERN_INPUTS_64_SHORT_COUNT) *
(PATTERN_INPUTS_64_SHORT_COUNT)) +
RANDOM_INPUTS_64_SHORT_COUNT * i + j));
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results_64(isa_ase_name, group_name, instruction_name,
TEST_COUNT_TOTAL, elapsed_time, b64_result,
b64_expect);
return ret;
}

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/*
* Test program for MIPS64R6 instruction CRC32CD
*
* Copyright (C) 2019 Wave Computing, Inc.
* Copyright (C) 2019 Aleksandar Markovic <amarkovic@wavecomp.com>
* Copyright (C) 2025 Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_mips64r6.h"
#include "../../../../include/test_inputs_64.h"
#include "../../../../include/test_utils_64.h"
#define TEST_COUNT_TOTAL (PATTERN_INPUTS_64_COUNT + RANDOM_INPUTS_64_COUNT)
int32_t main(void)
{
char *isa_ase_name = "mips64r6";
char *group_name = "CRC with reversed polynomial 0x82F63B78";
char *instruction_name = "CRC32CD";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b64_result[TEST_COUNT_TOTAL];
uint64_t b64_expect[TEST_COUNT_TOTAL] = {
0xffffffffb798b438ULL, /* 0 */
0xffffffffc44ff94dULL,
0xffffffff992a70ebULL,
0xffffffffeafd3d9eULL,
0x000000005152da26ULL,
0x0000000022859753ULL,
0x0000000015cb6d32ULL,
0x00000000661c2047ULL,
0x0000000073d74d75ULL, /* 8 */
0x0000000000000000ULL,
0x000000005d6589a6ULL,
0x000000002eb2c4d3ULL,
0xffffffff951d236bULL,
0xffffffffe6ca6e1eULL,
0xffffffffd184947fULL,
0xffffffffa253d90aULL,
0x0000000008f9ceacULL, /* 16 */
0x000000007b2e83d9ULL,
0x00000000264b0a7fULL,
0x00000000559c470aULL,
0xffffffffee33a0b2ULL,
0xffffffff9de4edc7ULL,
0xffffffffaaaa17a6ULL,
0xffffffffd97d5ad3ULL,
0xffffffffccb637e1ULL, /* 24 */
0xffffffffbf617a94ULL,
0xffffffffe204f332ULL,
0xffffffff91d3be47ULL,
0x000000002a7c59ffULL,
0x0000000059ab148aULL,
0x000000006ee5eeebULL,
0x000000001d32a39eULL,
0x0000000021e3b01bULL, /* 32 */
0x000000005234fd6eULL,
0x000000000f5174c8ULL,
0x000000007c8639bdULL,
0xffffffffc729de05ULL,
0xffffffffb4fe9370ULL,
0xffffffff83b06911ULL,
0xfffffffff0672464ULL,
0xffffffffe5ac4956ULL, /* 40 */
0xffffffff967b0423ULL,
0xffffffffcb1e8d85ULL,
0xffffffffb8c9c0f0ULL,
0x0000000003662748ULL,
0x0000000070b16a3dULL,
0x0000000047ff905cULL,
0x000000003428dd29ULL,
0xffffffffb89d59a6ULL, /* 48 */
0xffffffffcb4a14d3ULL,
0xffffffff962f9d75ULL,
0xffffffffe5f8d000ULL,
0x000000005e5737b8ULL,
0x000000002d807acdULL,
0x000000001ace80acULL,
0x000000006919cdd9ULL,
0x000000007cd2a0ebULL, /* 56 */
0x000000000f05ed9eULL,
0x0000000052606438ULL,
0x0000000021b7294dULL,
0xffffffff9a18cef5ULL,
0xffffffffe9cf8380ULL,
0xffffffffde8179e1ULL,
0xffffffffad563494ULL,
0x000000003a358bb3ULL, /* 64 */
0xffffffff975446ebULL,
0x0000000041d37ad6ULL,
0x000000004be84fe1ULL,
0xffffffff9671b1b3ULL,
0x000000003b107cebULL,
0xffffffffed9740d6ULL,
0xffffffffe7ac75e1ULL,
0xffffffffa1489696ULL, /* 72 */
0x000000000c295bceULL,
0xffffffffdaae67f3ULL,
0xffffffffd09552c4ULL,
0x0000000042bd7071ULL,
0xffffffffefdcbd29ULL,
0x00000000395b8114ULL,
0x000000003360b423ULL,
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_CRC32CD(b64_pattern + i, b64_pattern + j,
b64_result + (PATTERN_INPUTS_64_SHORT_COUNT * i + j));
}
}
for (i = 0; i < RANDOM_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_CRC32CD(b64_random + i, b64_random + j,
b64_result + (((PATTERN_INPUTS_64_SHORT_COUNT) *
(PATTERN_INPUTS_64_SHORT_COUNT)) +
RANDOM_INPUTS_64_SHORT_COUNT * i + j));
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results_64(isa_ase_name, group_name, instruction_name,
TEST_COUNT_TOTAL, elapsed_time, b64_result,
b64_expect);
return ret;
}

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/*
* Test program for MIPS64R6 instruction CRC32CH
*
* Copyright (C) 2019 Wave Computing, Inc.
* Copyright (C) 2019 Aleksandar Markovic <amarkovic@wavecomp.com>
* Copyright (C) 2025 Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_mips64r6.h"
#include "../../../../include/test_inputs_64.h"
#include "../../../../include/test_utils_64.h"
#define TEST_COUNT_TOTAL (PATTERN_INPUTS_64_COUNT + RANDOM_INPUTS_64_COUNT)
int32_t main(void)
{
char *isa_ase_name = "mips64r6";
char *group_name = "CRC with reversed polynomial 0x82F63B78";
char *instruction_name = "CRC32CH";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b64_result[TEST_COUNT_TOTAL];
uint64_t b64_expect[TEST_COUNT_TOTAL] = {
0x000000000000ffffULL, /* 0 */
0x000000000e9e77d2ULL,
0xfffffffff92eaa4bULL,
0xfffffffff7b02266ULL,
0x00000000571acc93ULL,
0x00000000598444beULL,
0xfffffffff1e6ca77ULL,
0xffffffffff78425aULL,
0x000000000e9e882dULL, /* 8 */
0x0000000000000000ULL,
0xfffffffff7b0dd99ULL,
0xfffffffff92e55b4ULL,
0x000000005984bb41ULL,
0x00000000571a336cULL,
0xffffffffff78bda5ULL,
0xfffffffff1e63588ULL,
0xfffffffff92eff1eULL, /* 16 */
0xfffffffff7b07733ULL,
0x000000000000aaaaULL,
0x000000000e9e2287ULL,
0xffffffffae34cc72ULL,
0xffffffffa0aa445fULL,
0x0000000008c8ca96ULL,
0x00000000065642bbULL,
0xfffffffff7b088ccULL, /* 24 */
0xfffffffff92e00e1ULL,
0x000000000e9edd78ULL,
0x0000000000005555ULL,
0xffffffffa0aabba0ULL,
0xffffffffae34338dULL,
0x000000000656bd44ULL,
0x0000000008c83569ULL,
0x00000000571affa0ULL, /* 32 */
0x000000005984778dULL,
0xffffffffae34aa14ULL,
0xffffffffa0aa2239ULL,
0x000000000000ccccULL,
0x000000000e9e44e1ULL,
0xffffffffa6fcca28ULL,
0xffffffffa8624205ULL,
0x0000000059848872ULL, /* 40 */
0x00000000571a005fULL,
0xffffffffa0aaddc6ULL,
0xffffffffae3455ebULL,
0x000000000e9ebb1eULL,
0x0000000000003333ULL,
0xffffffffa862bdfaULL,
0xffffffffa6fc35d7ULL,
0xfffffffff1e6bbb0ULL, /* 48 */
0xffffffffff78339dULL,
0x0000000008c8ee04ULL,
0x0000000006566629ULL,
0xffffffffa6fc88dcULL,
0xffffffffa86200f1ULL,
0x0000000000008e38ULL,
0x000000000e9e0615ULL,
0xffffffffff78cc62ULL, /* 56 */
0xfffffffff1e6444fULL,
0x00000000065699d6ULL,
0x0000000008c811fbULL,
0xffffffffa862ff0eULL,
0xffffffffa6fc7723ULL,
0x000000000e9ef9eaULL,
0x00000000000071c7ULL,
0x0000000000002862ULL, /* 64 */
0x000000001190c4cfULL,
0x000000007b7fdbbeULL,
0xffffffff9204da99ULL,
0x000000001190a13eULL,
0x0000000000004d93ULL,
0x000000006aef52e2ULL,
0xffffffff839453c5ULL,
0x000000007b7f4a13ULL, /* 72 */
0x000000006aefa6beULL,
0x000000000000b9cfULL,
0xffffffffe97bb8e8ULL,
0xffffffff9204accaULL,
0xffffffff83944067ULL,
0xffffffffe97b5f16ULL,
0x0000000000005e31ULL,
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_CRC32CH(b64_pattern + i, b64_pattern + j,
b64_result + (PATTERN_INPUTS_64_SHORT_COUNT * i + j));
}
}
for (i = 0; i < RANDOM_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_CRC32CH(b64_random + i, b64_random + j,
b64_result + (((PATTERN_INPUTS_64_SHORT_COUNT) *
(PATTERN_INPUTS_64_SHORT_COUNT)) +
RANDOM_INPUTS_64_SHORT_COUNT * i + j));
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results_64(isa_ase_name, group_name, instruction_name,
TEST_COUNT_TOTAL, elapsed_time, b64_result,
b64_expect);
return ret;
}

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/*
* Test program for MIPS64R6 instruction CRC32CW
*
* Copyright (C) 2019 Wave Computing, Inc.
* Copyright (C) 2019 Aleksandar Markovic <amarkovic@wavecomp.com>
* Copyright (C) 2025 Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_mips64r6.h"
#include "../../../../include/test_inputs_64.h"
#include "../../../../include/test_utils_64.h"
#define TEST_COUNT_TOTAL (PATTERN_INPUTS_64_COUNT + RANDOM_INPUTS_64_COUNT)
int32_t main(void)
{
char *isa_ase_name = "mips64r6";
char *group_name = "CRC with reversed polynomial 0x82F63B78";
char *instruction_name = "CRC32CW";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b64_result[TEST_COUNT_TOTAL];
uint64_t b64_expect[TEST_COUNT_TOTAL] = {
0x0000000000000000ULL, /* 0 */
0xffffffffb798b438ULL,
0xffffffff91d3be47ULL,
0x00000000264b0a7fULL,
0x0000000070b16a3dULL,
0xffffffffc729de05ULL,
0x0000000063c5950aULL,
0xffffffffd45d2132ULL,
0xffffffffb798b438ULL, /* 8 */
0x0000000000000000ULL,
0x00000000264b0a7fULL,
0xffffffff91d3be47ULL,
0xffffffffc729de05ULL,
0x0000000070b16a3dULL,
0xffffffffd45d2132ULL,
0x0000000063c5950aULL,
0xffffffff91d3be47ULL, /* 16 */
0x00000000264b0a7fULL,
0x0000000000000000ULL,
0xffffffffb798b438ULL,
0xffffffffe162d47aULL,
0x0000000056fa6042ULL,
0xfffffffff2162b4dULL,
0x00000000458e9f75ULL,
0x00000000264b0a7fULL, /* 24 */
0xffffffff91d3be47ULL,
0xffffffffb798b438ULL,
0x0000000000000000ULL,
0x0000000056fa6042ULL,
0xffffffffe162d47aULL,
0x00000000458e9f75ULL,
0xfffffffff2162b4dULL,
0x0000000070b16a3dULL, /* 32 */
0xffffffffc729de05ULL,
0xffffffffe162d47aULL,
0x0000000056fa6042ULL,
0x0000000000000000ULL,
0xffffffffb798b438ULL,
0x000000001374ff37ULL,
0xffffffffa4ec4b0fULL,
0xffffffffc729de05ULL, /* 40 */
0x0000000070b16a3dULL,
0x0000000056fa6042ULL,
0xffffffffe162d47aULL,
0xffffffffb798b438ULL,
0x0000000000000000ULL,
0xffffffffa4ec4b0fULL,
0x000000001374ff37ULL,
0x0000000063c5950aULL, /* 48 */
0xffffffffd45d2132ULL,
0xfffffffff2162b4dULL,
0x00000000458e9f75ULL,
0x000000001374ff37ULL,
0xffffffffa4ec4b0fULL,
0x0000000000000000ULL,
0xffffffffb798b438ULL,
0xffffffffd45d2132ULL, /* 56 */
0x0000000063c5950aULL,
0x00000000458e9f75ULL,
0xfffffffff2162b4dULL,
0xffffffffa4ec4b0fULL,
0x000000001374ff37ULL,
0xffffffffb798b438ULL,
0x0000000000000000ULL,
0x0000000000000000ULL, /* 64 */
0xffffffffea0755b2ULL,
0x0000000008b188e6ULL,
0xffffffffff3cc8d9ULL,
0xffffffffea0755b2ULL,
0x0000000000000000ULL,
0xffffffffe2b6dd54ULL,
0x00000000153b9d6bULL,
0x0000000008b188e6ULL, /* 72 */
0xffffffffe2b6dd54ULL,
0x0000000000000000ULL,
0xfffffffff78d403fULL,
0xffffffffff3cc8d9ULL,
0x00000000153b9d6bULL,
0xfffffffff78d403fULL,
0x0000000000000000ULL,
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_CRC32CW(b64_pattern + i, b64_pattern + j,
b64_result + (PATTERN_INPUTS_64_SHORT_COUNT * i + j));
}
}
for (i = 0; i < RANDOM_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_CRC32CW(b64_random + i, b64_random + j,
b64_result + (((PATTERN_INPUTS_64_SHORT_COUNT) *
(PATTERN_INPUTS_64_SHORT_COUNT)) +
RANDOM_INPUTS_64_SHORT_COUNT * i + j));
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results_64(isa_ase_name, group_name, instruction_name,
TEST_COUNT_TOTAL, elapsed_time, b64_result,
b64_expect);
return ret;
}

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/*
* Test program for MIPS64R6 instruction CRC32D
*
* Copyright (C) 2019 Wave Computing, Inc.
* Copyright (C) 2019 Aleksandar Markovic <amarkovic@wavecomp.com>
* Copyright (C) 2025 Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_mips64r6.h"
#include "../../../../include/test_inputs_64.h"
#include "../../../../include/test_utils_64.h"
#define TEST_COUNT_TOTAL (PATTERN_INPUTS_64_COUNT + RANDOM_INPUTS_64_COUNT)
int32_t main(void)
{
char *isa_ase_name = "mips64r6";
char *group_name = "CRC with reversed polynomial 0xEDB88320";
char *instruction_name = "CRC32D";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b64_result[TEST_COUNT_TOTAL];
uint64_t b64_expect[TEST_COUNT_TOTAL] = {
0xffffffffdebb20e3ULL, /* 0 */
0x0000000044660075ULL,
0x000000001e20c2aeULL,
0xffffffff84fde238ULL,
0x00000000281d7ce7ULL,
0xffffffffb2c05c71ULL,
0xffffffffd660a024ULL,
0x000000004cbd80b2ULL,
0xffffffff9add2096ULL, /* 8 */
0x0000000000000000ULL,
0x000000005a46c2dbULL,
0xffffffffc09be24dULL,
0x000000006c7b7c92ULL,
0xfffffffff6a65c04ULL,
0xffffffff9206a051ULL,
0x0000000008db80c7ULL,
0x000000005449dd0fULL, /* 16 */
0xffffffffce94fd99ULL,
0xffffffff94d23f42ULL,
0x000000000e0f1fd4ULL,
0xffffffffa2ef810bULL,
0x000000003832a19dULL,
0x000000005c925dc8ULL,
0xffffffffc64f7d5eULL,
0x00000000102fdd7aULL, /* 24 */
0xffffffff8af2fdecULL,
0xffffffffd0b43f37ULL,
0x000000004a691fa1ULL,
0xffffffffe689817eULL,
0x000000007c54a1e8ULL,
0x0000000018f45dbdULL,
0xffffffff82297d2bULL,
0xffffffffa7157447ULL, /* 32 */
0x000000003dc854d1ULL,
0x00000000678e960aULL,
0xfffffffffd53b69cULL,
0x0000000051b32843ULL,
0xffffffffcb6e08d5ULL,
0xffffffffafcef480ULL,
0x000000003513d416ULL,
0xffffffffe3737432ULL, /* 40 */
0x0000000079ae54a4ULL,
0x0000000023e8967fULL,
0xffffffffb935b6e9ULL,
0x0000000015d52836ULL,
0xffffffff8f0808a0ULL,
0xffffffffeba8f4f5ULL,
0x000000007175d463ULL,
0x000000007a6adc3eULL, /* 48 */
0xffffffffe0b7fca8ULL,
0xffffffffbaf13e73ULL,
0x00000000202c1ee5ULL,
0xffffffff8ccc803aULL,
0x000000001611a0acULL,
0x0000000072b15cf9ULL,
0xffffffffe86c7c6fULL,
0x000000003e0cdc4bULL, /* 56 */
0xffffffffa4d1fcddULL,
0xfffffffffe973e06ULL,
0x00000000644a1e90ULL,
0xffffffffc8aa804fULL,
0x000000005277a0d9ULL,
0x0000000036d75c8cULL,
0xffffffffac0a7c1aULL,
0xffffffffed857593ULL, /* 64 */
0xffffffffe0b6f95fULL,
0x00000000253b462cULL,
0xffffffffe15579b9ULL,
0x0000000074897c83ULL,
0x0000000079baf04fULL,
0xffffffffbc374f3cULL,
0x00000000785970a9ULL,
0xffffffffa6bae0a9ULL, /* 72 */
0xffffffffab896c65ULL,
0x000000006e04d316ULL,
0xffffffffaa6aec83ULL,
0x000000005ae171feULL,
0x0000000057d2fd32ULL,
0xffffffff925f4241ULL,
0x0000000056317dd4ULL,
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_CRC32D(b64_pattern + i, b64_pattern + j,
b64_result + (PATTERN_INPUTS_64_SHORT_COUNT * i + j));
}
}
for (i = 0; i < RANDOM_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_CRC32D(b64_random + i, b64_random + j,
b64_result + (((PATTERN_INPUTS_64_SHORT_COUNT) *
(PATTERN_INPUTS_64_SHORT_COUNT)) +
RANDOM_INPUTS_64_SHORT_COUNT * i + j));
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results_64(isa_ase_name, group_name, instruction_name,
TEST_COUNT_TOTAL, elapsed_time, b64_result,
b64_expect);
return ret;
}

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/*
* Test program for MIPS64R6 instruction CRC32H
*
* Copyright (C) 2019 Wave Computing, Inc.
* Copyright (C) 2019 Aleksandar Markovic <amarkovic@wavecomp.com>
* Copyright (C) 2025 Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_mips64r6.h"
#include "../../../../include/test_inputs_64.h"
#include "../../../../include/test_utils_64.h"
#define TEST_COUNT_TOTAL (PATTERN_INPUTS_64_COUNT + RANDOM_INPUTS_64_COUNT)
int32_t main(void)
{
char *isa_ase_name = "mips64r6";
char *group_name = "CRC with reversed polynomial 0xEDB88320";
char *instruction_name = "CRC32H";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b64_result[TEST_COUNT_TOTAL];
uint64_t b64_expect[TEST_COUNT_TOTAL] = {
0x000000000000ffffULL, /* 0 */
0xffffffffbe2612ffULL,
0xffffffffdccda6c0ULL,
0x0000000062eb4bc0ULL,
0x000000004bbbc8eaULL,
0xfffffffff59d25eaULL,
0x0000000022259ac0ULL,
0xffffffff9c0377c0ULL,
0xffffffffbe26ed00ULL, /* 8 */
0x0000000000000000ULL,
0x0000000062ebb43fULL,
0xffffffffdccd593fULL,
0xfffffffff59dda15ULL,
0x000000004bbb3715ULL,
0xffffffff9c03883fULL,
0x000000002225653fULL,
0xffffffffdccdf395ULL, /* 16 */
0x0000000062eb1e95ULL,
0x000000000000aaaaULL,
0xffffffffbe2647aaULL,
0xffffffff9776c480ULL,
0x0000000029502980ULL,
0xfffffffffee896aaULL,
0x0000000040ce7baaULL,
0x0000000062ebe16aULL, /* 24 */
0xffffffffdccd0c6aULL,
0xffffffffbe26b855ULL,
0x0000000000005555ULL,
0x000000002950d67fULL,
0xffffffff97763b7fULL,
0x0000000040ce8455ULL,
0xfffffffffee86955ULL,
0x000000004bbbfbd9ULL, /* 32 */
0xfffffffff59d16d9ULL,
0xffffffff9776a2e6ULL,
0x0000000029504fe6ULL,
0x000000000000ccccULL,
0xffffffffbe2621ccULL,
0x00000000699e9ee6ULL,
0xffffffffd7b873e6ULL,
0xfffffffff59de926ULL, /* 40 */
0x000000004bbb0426ULL,
0x000000002950b019ULL,
0xffffffff97765d19ULL,
0xffffffffbe26de33ULL,
0x0000000000003333ULL,
0xffffffffd7b88c19ULL,
0x00000000699e6119ULL,
0x000000002225eb07ULL, /* 48 */
0xffffffff9c030607ULL,
0xfffffffffee8b238ULL,
0x0000000040ce5f38ULL,
0x00000000699edc12ULL,
0xffffffffd7b83112ULL,
0x0000000000008e38ULL,
0xffffffffbe266338ULL,
0xffffffff9c03f9f8ULL, /* 56 */
0x00000000222514f8ULL,
0x0000000040cea0c7ULL,
0xfffffffffee84dc7ULL,
0xffffffffd7b8ceedULL,
0x00000000699e23edULL,
0xffffffffbe269cc7ULL,
0x00000000000071c7ULL,
0x0000000000002862ULL, /* 64 */
0x0000000026a17af6ULL,
0xffffffffaa919152ULL,
0xffffffffcb865590ULL,
0x0000000026a11f07ULL,
0x0000000000004d93ULL,
0xffffffff8c30a637ULL,
0xffffffffed2762f5ULL,
0xffffffffaa9100ffULL, /* 72 */
0xffffffff8c30526bULL,
0x000000000000b9cfULL,
0x0000000061177d0dULL,
0xffffffffcb8623c3ULL,
0xffffffffed277157ULL,
0x0000000061179af3ULL,
0x0000000000005e31ULL
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_CRC32H(b64_pattern + i, b64_pattern + j,
b64_result + (PATTERN_INPUTS_64_SHORT_COUNT * i + j));
}
}
for (i = 0; i < RANDOM_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_CRC32H(b64_random + i, b64_random + j,
b64_result + (((PATTERN_INPUTS_64_SHORT_COUNT) *
(PATTERN_INPUTS_64_SHORT_COUNT)) +
RANDOM_INPUTS_64_SHORT_COUNT * i + j));
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results_64(isa_ase_name, group_name, instruction_name,
TEST_COUNT_TOTAL, elapsed_time, b64_result,
b64_expect);
return ret;
}

142
tests/tcg/mips/user/isa/mips64r6/crc/test_mips64r6_crc32w.c Normal file
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/*
* Test program for MIPS64R6 instruction CRC32W
*
* Copyright (C) 2019 Wave Computing, Inc.
* Copyright (C) 2019 Aleksandar Markovic <amarkovic@wavecomp.com>
* Copyright (C) 2025 Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <sys/time.h>
#include <stdint.h>
#include "../../../../include/wrappers_mips64r6.h"
#include "../../../../include/test_inputs_64.h"
#include "../../../../include/test_utils_64.h"
#define TEST_COUNT_TOTAL (PATTERN_INPUTS_64_COUNT + RANDOM_INPUTS_64_COUNT)
int32_t main(void)
{
char *isa_ase_name = "mips64r6";
char *group_name = "CRC with reversed polynomial 0xEDB88320";
char *instruction_name = "CRC32W";
int32_t ret;
uint32_t i, j;
struct timeval start, end;
double elapsed_time;
uint64_t b64_result[TEST_COUNT_TOTAL];
uint64_t b64_expect[TEST_COUNT_TOTAL] = {
0x0000000000000000ULL, /* 0 */
0xffffffffdebb20e3ULL,
0x000000004a691fa1ULL,
0xffffffff94d23f42ULL,
0xffffffff8f0808a0ULL,
0x0000000051b32843ULL,
0x0000000065069dceULL,
0xffffffffbbbdbd2dULL,
0xffffffffdebb20e3ULL, /* 8 */
0x0000000000000000ULL,
0xffffffff94d23f42ULL,
0x000000004a691fa1ULL,
0x0000000051b32843ULL,
0xffffffff8f0808a0ULL,
0xffffffffbbbdbd2dULL,
0x0000000065069dceULL,
0x000000004a691fa1ULL, /* 16 */
0xffffffff94d23f42ULL,
0x0000000000000000ULL,
0xffffffffdebb20e3ULL,
0xffffffffc5611701ULL,
0x000000001bda37e2ULL,
0x000000002f6f826fULL,
0xfffffffff1d4a28cULL,
0xffffffff94d23f42ULL, /* 24 */
0x000000004a691fa1ULL,
0xffffffffdebb20e3ULL,
0x0000000000000000ULL,
0x000000001bda37e2ULL,
0xffffffffc5611701ULL,
0xfffffffff1d4a28cULL,
0x000000002f6f826fULL,
0xffffffff8f0808a0ULL, /* 32 */
0x0000000051b32843ULL,
0xffffffffc5611701ULL,
0x000000001bda37e2ULL,
0x0000000000000000ULL,
0xffffffffdebb20e3ULL,
0xffffffffea0e956eULL,
0x0000000034b5b58dULL,
0x0000000051b32843ULL, /* 40 */
0xffffffff8f0808a0ULL,
0x000000001bda37e2ULL,
0xffffffffc5611701ULL,
0xffffffffdebb20e3ULL,
0x0000000000000000ULL,
0x0000000034b5b58dULL,
0xffffffffea0e956eULL,
0x0000000065069dceULL, /* 48 */
0xffffffffbbbdbd2dULL,
0x000000002f6f826fULL,
0xfffffffff1d4a28cULL,
0xffffffffea0e956eULL,
0x0000000034b5b58dULL,
0x0000000000000000ULL,
0xffffffffdebb20e3ULL,
0xffffffffbbbdbd2dULL, /* 56 */
0x0000000065069dceULL,
0xfffffffff1d4a28cULL,
0x000000002f6f826fULL,
0x0000000034b5b58dULL,
0xffffffffea0e956eULL,
0xffffffffdebb20e3ULL,
0x0000000000000000ULL,
0x0000000000000000ULL, /* 64 */
0xffffffff90485967ULL,
0x000000006dfb974aULL,
0x00000000083e4538ULL,
0xffffffff90485967ULL,
0x0000000000000000ULL,
0xfffffffffdb3ce2dULL,
0xffffffff98761c5fULL,
0x000000006dfb974aULL, /* 72 */
0xfffffffffdb3ce2dULL,
0x0000000000000000ULL,
0x0000000065c5d272ULL,
0x00000000083e4538ULL,
0xffffffff98761c5fULL,
0x0000000065c5d272ULL,
0x0000000000000000ULL,
};
gettimeofday(&start, NULL);
for (i = 0; i < PATTERN_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < PATTERN_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_CRC32W(b64_pattern + i, b64_pattern + j,
b64_result + (PATTERN_INPUTS_64_SHORT_COUNT * i + j));
}
}
for (i = 0; i < RANDOM_INPUTS_64_SHORT_COUNT; i++) {
for (j = 0; j < RANDOM_INPUTS_64_SHORT_COUNT; j++) {
do_mips64r6_CRC32W(b64_random + i, b64_random + j,
b64_result + (((PATTERN_INPUTS_64_SHORT_COUNT) *
(PATTERN_INPUTS_64_SHORT_COUNT)) +
RANDOM_INPUTS_64_SHORT_COUNT * i + j));
}
}
gettimeofday(&end, NULL);
elapsed_time = (end.tv_sec - start.tv_sec) * 1000.0;
elapsed_time += (end.tv_usec - start.tv_usec) / 1000.0;
ret = check_results_64(isa_ase_name, group_name, instruction_name,
TEST_COUNT_TOTAL, elapsed_time, b64_result,
b64_expect);
return ret;
}