hw/misc/aspeed_scu: Support the Frequency Counter Control register for AST2700
According to the datasheet: BIT[1] (SCU_FREQ_OSC_EN) enables the oscillator frequency measurement counter. BIT[6] (SCU_FREQ_DONE) indicates the measurement is finished. Firmware polls BIT[6] to determine when measurement is complete. The flag can be cleared by writing BIT[1] to 0. To simulate this hardware behavior in QEMU: If BIT[1] is set to 1, BIT[6] is immediately set to 1 to avoid firmware hanging during polling. If BIT[1] is cleared to 0, BIT[6] is also cleared to 0 to match hardware semantics. The initial value of this register is initialized to 0x80, reflecting the default value confirmed from an EVB register dump. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250618080006.846355-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
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1 changed files with 6 additions and 0 deletions
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@ -176,6 +176,7 @@
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#define AST2700_SCUIO_UARTCLK_GEN TO_REG(0x330)
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#define AST2700_SCUIO_HUARTCLK_GEN TO_REG(0x334)
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#define AST2700_SCUIO_CLK_DUTY_MEAS_RST TO_REG(0x388)
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#define AST2700_SCUIO_FREQ_CNT_CTL TO_REG(0x3A0)
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#define SCU_IO_REGION_SIZE 0x1000
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@ -1022,6 +1023,10 @@ static void aspeed_ast2700_scuio_write(void *opaque, hwaddr offset,
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s->regs[reg - 1] ^= data;
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updated = true;
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break;
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case AST2700_SCUIO_FREQ_CNT_CTL:
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s->regs[reg] = deposit32(s->regs[reg], 6, 1, !!(data & BIT(1)));
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updated = true;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
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@ -1066,6 +1071,7 @@ static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] = {
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[AST2700_SCUIO_UARTCLK_GEN] = 0x00014506,
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[AST2700_SCUIO_HUARTCLK_GEN] = 0x000145c0,
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[AST2700_SCUIO_CLK_DUTY_MEAS_RST] = 0x0c9100d2,
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[AST2700_SCUIO_FREQ_CNT_CTL] = 0x00000080,
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};
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static void aspeed_2700_scuio_class_init(ObjectClass *klass, const void *data)
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