amd_iommu: Add helpers to walk AMD v1 Page Table format
The current amdvi_page_walk() is designed to be called by the replay() method. Rather than drastically altering it, introduce helpers to fetch guest PTEs that will be used by a page walker implementation. Signed-off-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250919213515.917111-8-alejandro.j.jimenez@oracle.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Alejandro Jimenez
Michael S. Tsirkin
parent
0f13cc5642
commit
a74bb3110a
2 changed files with 163 additions and 0 deletions
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@ -87,6 +87,8 @@ typedef enum AMDVIFaultReason {
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AMDVI_FR_DTE_RTR_ERR = 1, /* Failure to retrieve DTE */
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AMDVI_FR_DTE_V, /* DTE[V] = 0 */
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AMDVI_FR_DTE_TV, /* DTE[TV] = 0 */
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AMDVI_FR_PT_ROOT_INV, /* Page Table Root ptr invalid */
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AMDVI_FR_PT_ENTRY_INV, /* Failure to read PTE from guest memory */
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} AMDVIFaultReason;
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uint64_t amdvi_extended_feature_register(AMDVIState *s)
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@ -558,6 +560,127 @@ static int amdvi_as_to_dte(AMDVIAddressSpace *as, uint64_t *dte)
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return 0;
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}
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/*
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* For a PTE encoding a large page, return the page size it encodes as described
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* by the AMD IOMMU Specification Table 14: Example Page Size Encodings.
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* No need to adjust the value of the PTE to point to the first PTE in the large
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* page since the encoding guarantees all "base" PTEs in the large page are the
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* same.
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*/
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static uint64_t large_pte_page_size(uint64_t pte)
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{
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assert(PTE_NEXT_LEVEL(pte) == 7);
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/* Determine size of the large/contiguous page encoded in the PTE */
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return PTE_LARGE_PAGE_SIZE(pte);
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}
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/*
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* Helper function to fetch a PTE using AMD v1 pgtable format.
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* On successful page walk, returns 0 and pte parameter points to a valid PTE.
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* On failure, returns:
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* -AMDVI_FR_PT_ROOT_INV: A page walk is not possible due to conditions like DTE
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* with invalid permissions, Page Table Root can not be read from DTE, or a
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* larger IOVA than supported by page table level encoded in DTE[Mode].
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* -AMDVI_FR_PT_ENTRY_INV: A PTE could not be read from guest memory during a
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* page table walk. This means that the DTE has valid data, but one of the
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* lower level entries in the Page Table could not be read.
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*/
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static int __attribute__((unused))
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fetch_pte(AMDVIAddressSpace *as, hwaddr address, uint64_t dte, uint64_t *pte,
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hwaddr *page_size)
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{
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IOMMUAccessFlags perms = amdvi_get_perms(dte);
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uint8_t level, mode;
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uint64_t pte_addr;
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*pte = dte;
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*page_size = 0;
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if (perms == IOMMU_NONE) {
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return -AMDVI_FR_PT_ROOT_INV;
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}
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/*
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* The Linux kernel driver initializes the default mode to 3, corresponding
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* to a 39-bit GPA space, where each entry in the pagetable translates to a
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* 1GB (2^30) page size.
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*/
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level = mode = get_pte_translation_mode(dte);
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assert(mode > 0 && mode < 7);
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/*
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* If IOVA is larger than the max supported by the current pgtable level,
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* there is nothing to do.
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*/
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if (address > PT_LEVEL_MAX_ADDR(mode - 1)) {
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/* IOVA too large for the current DTE */
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return -AMDVI_FR_PT_ROOT_INV;
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}
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do {
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level -= 1;
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/* Update the page_size */
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*page_size = PTE_LEVEL_PAGE_SIZE(level);
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/* Permission bits are ANDed at every level, including the DTE */
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perms &= amdvi_get_perms(*pte);
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if (perms == IOMMU_NONE) {
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return 0;
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}
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/* Not Present */
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if (!IOMMU_PTE_PRESENT(*pte)) {
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return 0;
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}
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/* Large or Leaf PTE found */
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if (PTE_NEXT_LEVEL(*pte) == 7 || PTE_NEXT_LEVEL(*pte) == 0) {
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/* Leaf PTE found */
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break;
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}
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/*
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* Index the pgtable using the IOVA bits corresponding to current level
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* and walk down to the lower level.
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*/
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pte_addr = NEXT_PTE_ADDR(*pte, level, address);
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*pte = amdvi_get_pte_entry(as->iommu_state, pte_addr, as->devfn);
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if (*pte == (uint64_t)-1) {
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/*
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* A returned PTE of -1 indicates a failure to read the page table
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* entry from guest memory.
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*/
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if (level == mode - 1) {
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/* Failure to retrieve the Page Table from Root Pointer */
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*page_size = 0;
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return -AMDVI_FR_PT_ROOT_INV;
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} else {
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/* Failure to read PTE. Page walk skips a page_size chunk */
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return -AMDVI_FR_PT_ENTRY_INV;
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}
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}
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} while (level > 0);
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assert(PTE_NEXT_LEVEL(*pte) == 0 || PTE_NEXT_LEVEL(*pte) == 7 ||
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level == 0);
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/*
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* Page walk ends when Next Level field on PTE shows that either a leaf PTE
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* or a series of large PTEs have been reached. In the latter case, even if
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* the range starts in the middle of a contiguous page, the returned PTE
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* must be the first PTE of the series.
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*/
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if (PTE_NEXT_LEVEL(*pte) == 7) {
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/* Update page_size with the large PTE page size */
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*page_size = large_pte_page_size(*pte);
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}
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return 0;
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}
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/* log error without aborting since linux seems to be using reserved bits */
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static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd)
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{
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@ -178,6 +178,46 @@
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#define AMDVI_GATS_MODE (2ULL << 12)
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#define AMDVI_HATS_MODE (2ULL << 10)
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/* Page Table format */
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#define AMDVI_PTE_PR (1ULL << 0)
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#define AMDVI_PTE_NEXT_LEVEL_MASK GENMASK64(11, 9)
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#define IOMMU_PTE_PRESENT(pte) ((pte) & AMDVI_PTE_PR)
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/* Using level=0 for leaf PTE at 4K page size */
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#define PT_LEVEL_SHIFT(level) (12 + ((level) * 9))
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/* Return IOVA bit group used to index the Page Table at specific level */
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#define PT_LEVEL_INDEX(level, iova) (((iova) >> PT_LEVEL_SHIFT(level)) & \
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GENMASK64(8, 0))
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/* Return the max address for a specified level i.e. max_oaddr */
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#define PT_LEVEL_MAX_ADDR(x) (((x) < 5) ? \
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((1ULL << PT_LEVEL_SHIFT((x + 1))) - 1) : \
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(~(0ULL)))
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/* Extract the NextLevel field from PTE/PDE */
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#define PTE_NEXT_LEVEL(pte) (((pte) & AMDVI_PTE_NEXT_LEVEL_MASK) >> 9)
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/* Take page table level and return default pagetable size for level */
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#define PTE_LEVEL_PAGE_SIZE(level) (1ULL << (PT_LEVEL_SHIFT(level)))
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/*
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* Return address of lower level page table encoded in PTE and specified by
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* current level and corresponding IOVA bit group at such level.
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*/
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#define NEXT_PTE_ADDR(pte, level, iova) (((pte) & AMDVI_DEV_PT_ROOT_MASK) + \
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(PT_LEVEL_INDEX(level, iova) * 8))
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/*
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* Take a PTE value with mode=0x07 and return the page size it encodes.
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*/
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#define PTE_LARGE_PAGE_SIZE(pte) (1ULL << (1 + cto64(((pte) | 0xfffULL))))
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/* Return number of PTEs to use for a given page size (expected power of 2) */
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#define PAGE_SIZE_PTE_COUNT(pgsz) (1ULL << ((ctz64(pgsz) - 12) % 9))
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/* IOTLB */
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#define AMDVI_IOTLB_MAX_SIZE 1024
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#define AMDVI_DEVID_SHIFT 36
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