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Misc HW patches

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Various fixes and cleanups:
 - Set FPCR exception flag bits for HPPA non-trapped exceptions
 - Convert VirtIONet::vlans from pointer to array
   and remove VMSTATE_BUFFER_POINTER_UNSAFE()
 - Remove redundant QOM typedef when OBJECT_DECLARE_SIMPLE_TYPE() is used
 - Have various QDev / SysBus helpers take a const device argument
 - Improve errors when loaders parse images
 - Remove IntelIOMMUState::dma_translation leftover
 - Remove most target_[u]long uses in hw/riscv/
 - Fix DS1225Y MemoryRegion owner
 - Simplification refactors on Raven PCI Host Bridge
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Merge tag 'hw-misc-20251028' of https://github.com/philmd/qemu into staging

Misc HW patches

Various fixes and cleanups:
- Set FPCR exception flag bits for HPPA non-trapped exceptions
- Convert VirtIONet::vlans from pointer to array
  and remove VMSTATE_BUFFER_POINTER_UNSAFE()
- Remove redundant QOM typedef when OBJECT_DECLARE_SIMPLE_TYPE() is used
- Have various QDev / SysBus helpers take a const device argument
- Improve errors when loaders parse images
- Remove IntelIOMMUState::dma_translation leftover
- Remove most target_[u]long uses in hw/riscv/
- Fix DS1225Y MemoryRegion owner
- Simplification refactors on Raven PCI Host Bridge

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# gpg: Signature made Tue 28 Oct 2025 08:47:27 AM CET
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'hw-misc-20251028' of https://github.com/philmd/qemu: (23 commits)
  hw/riscv: Widen OpenSBI dynamic info struct
  hw/riscv: Use generic hwaddr for firmware addresses
  hw/i386/intel_iommu: Remove an unused state field
  nw/nvram/ds1225y: Fix nvram MemoryRegion owner
  hw/ppc: Pass error_fatal to load_image_targphys()
  hw/core/loader: Pass errp to load_image_targphys_as()
  hw/core/loader: add check for zero size in load_image_targphys_as
  hw/core/loader: improve error handling in image loading functions
  hw/core/loader: capture Error from load_image_targphys
  hw/core/loader: Use qemu_open() instead of open() in get_image_size()
  hw/int/loongarch: Include missing 'system/memory.h' header
  hw/uefi: Include missing 'system/memory.h' header
  hw/sysbus: Have various helpers take a const SysBusDevice argument
  hw/qdev: Have qdev_get_gpio_out_connector() take const DeviceState arg
  hw/pci-host/raven: Simplify PCI bus creation
  hw/pci-host/raven: Use DEFINE_TYPES macro
  hw/pci-host/raven: Simplify host bridge type declaration
  hw/pci-host/raven: Simplify PCI facing part
  hw/pci-host/raven: Simplify creating PCI facing part
  migration/vmstate: remove VMSTATE_BUFFER_POINTER_UNSAFE macro
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-10-28 11:48:05 +01:00
commit bc831f3739
97 changed files with 321 additions and 434 deletions
Download patch file Download diff file Expand all files Collapse all files

1
include/hw/char/serial.h
View file

@ -77,7 +77,6 @@ struct SerialState {
QEMUTimer *modem_status_poll;
MemoryRegion io;
};
typedef struct SerialState SerialState;
extern const VMStateDescription vmstate_serial;
extern const MemoryRegionOps serial_io_ops;

1
include/hw/i386/intel_iommu.h
View file

@ -307,7 +307,6 @@ struct IntelIOMMUState {
bool buggy_eim; /* Force buggy EIM unless eim=off */
uint8_t aw_bits; /* Host/IOVA address width (in bits) */
bool dma_drain; /* Whether DMA r/w draining enabled */
bool dma_translation; /* Whether DMA translation supported */
bool pasid; /* Whether to support PASID */
bool fs1gp; /* First Stage 1-GByte Page Support */

6
include/hw/input/lasips2.h
View file

@ -32,7 +32,8 @@ struct LASIPS2PortDeviceClass {
DeviceRealize parent_realize;
};
typedef struct LASIPS2State LASIPS2State;
#define TYPE_LASIPS2 "lasips2"
OBJECT_DECLARE_SIMPLE_TYPE(LASIPS2State, LASIPS2)
struct LASIPS2Port {
DeviceState parent_obj;
@ -74,7 +75,4 @@ struct LASIPS2State {
qemu_irq irq;
};
#define TYPE_LASIPS2 "lasips2"
OBJECT_DECLARE_SIMPLE_TYPE(LASIPS2State, LASIPS2)
#endif /* HW_INPUT_LASIPS2_H */

2
include/hw/intc/loongarch_dintc.h
View file

@ -8,7 +8,7 @@
#include "qom/object.h"
#include "hw/sysbus.h"
#include "hw/loongarch/virt.h"
#include "system/memory.h"
#define NR_VECTORS 256

1
include/hw/intc/loongarch_extioi_common.h
View file

@ -10,6 +10,7 @@
#include "qom/object.h"
#include "hw/sysbus.h"
#include "hw/loongarch/virt.h"
#include "system/memory.h"
#define LS3A_INTC_IP 8
#define EXTIOI_IRQS (256)

1
include/hw/intc/loongarch_pch_msi.h
View file

@ -6,6 +6,7 @@
*/
#include "hw/sysbus.h"
#include "system/memory.h"
#define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi"
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI)

1
include/hw/intc/loongarch_pic_common.h
View file

@ -9,6 +9,7 @@
#include "hw/loongarch/virt.h"
#include "hw/sysbus.h"
#include "system/memory.h"
#define PCH_PIC_INT_ID 0x00
#define PCH_PIC_INT_ID_VAL 0x7

1
include/hw/intc/loongson_ipi_common.h
View file

@ -11,6 +11,7 @@
#include "qom/object.h"
#include "hw/sysbus.h"
#include "exec/memattrs.h"
#include "system/memory.h"
#define IPI_MBX_NUM 4

8
include/hw/loader.h
View file

@ -1,6 +1,7 @@
#ifndef LOADER_H
#define LOADER_H
#include "hw/nvram/fw_cfg.h"
#include "qemu/typedefs.h"
/* loader.c */
/**
@ -10,7 +11,7 @@
* Returns the size of the image file on success, -1 otherwise.
* On error, errno is also set as appropriate.
*/
int64_t get_image_size(const char *filename);
int64_t get_image_size(const char *filename, Error **errp);
/**
* load_image_size: load an image file into specified buffer
* @filename: Path to the image file
@ -41,7 +42,8 @@ ssize_t load_image_size(const char *filename, void *addr, size_t size);
* Returns the size of the loaded image on success, -1 otherwise.
*/
ssize_t load_image_targphys_as(const char *filename,
hwaddr addr, uint64_t max_sz, AddressSpace *as);
hwaddr addr, uint64_t max_sz, AddressSpace *as,
Error **errp);
/**load_targphys_hex_as:
* @filename: Path to the .hex file
@ -61,7 +63,7 @@ ssize_t load_targphys_hex_as(const char *filename, hwaddr *entry,
* an AddressSpace.
*/
ssize_t load_image_targphys(const char *filename, hwaddr,
uint64_t max_sz);
uint64_t max_sz, Error **errp);
/**
* load_image_mr: load an image into a memory region

7
include/hw/misc/auxbus.h
View file

@ -29,13 +29,15 @@
#include "hw/qdev-core.h"
#include "qom/object.h"
typedef struct AUXSlave AUXSlave;
typedef enum AUXCommand AUXCommand;
typedef enum AUXReply AUXReply;
#define TYPE_AUXTOI2C "aux-to-i2c-bridge"
OBJECT_DECLARE_SIMPLE_TYPE(AUXTOI2CState, AUXTOI2C)
#define TYPE_AUX_SLAVE "aux-slave"
OBJECT_DECLARE_SIMPLE_TYPE(AUXSlave, AUX_SLAVE)
enum AUXCommand {
WRITE_I2C = 0,
READ_I2C = 1,
@ -73,9 +75,6 @@ struct AUXBus {
AddressSpace aux_addr_space;
};
#define TYPE_AUX_SLAVE "aux-slave"
OBJECT_DECLARE_SIMPLE_TYPE(AUXSlave, AUX_SLAVE)
struct AUXSlave {
/* < private > */
DeviceState parent_obj;

7
include/hw/misc/bcm2835_mphi.h
View file

@ -23,7 +23,8 @@
#define MPHI_MMIO_SIZE 0x1000
typedef struct BCM2835MphiState BCM2835MphiState;
#define TYPE_BCM2835_MPHI "bcm2835-mphi"
OBJECT_DECLARE_SIMPLE_TYPE(BCM2835MphiState, BCM2835_MPHI)
struct BCM2835MphiState {
SysBusDevice parent_obj;
@ -37,8 +38,4 @@ struct BCM2835MphiState {
uint32_t swirq;
};
#define TYPE_BCM2835_MPHI "bcm2835-mphi"
OBJECT_DECLARE_SIMPLE_TYPE(BCM2835MphiState, BCM2835_MPHI)
#endif

7
include/hw/misc/npcm7xx_pwm.h
View file

@ -35,8 +35,8 @@
* value of 100,000 the duty cycle for that PWM is 10%.
*/
#define NPCM7XX_PWM_MAX_DUTY 1000000
typedef struct NPCM7xxPWMState NPCM7xxPWMState;
#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxPWMState, NPCM7XX_PWM)
/**
* struct NPCM7xxPWM - The state of a single PWM channel.
@ -100,7 +100,4 @@ struct NPCM7xxPWMState {
uint32_t piir;
};
#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxPWMState, NPCM7XX_PWM)
#endif /* NPCM7XX_PWM_H */

6
include/hw/pci-host/pnv_phb3.h
View file

@ -14,7 +14,8 @@
#include "qom/object.h"
#include "hw/pci-host/pnv_phb.h"
typedef struct PnvPHB3 PnvPHB3;
#define TYPE_PNV_PHB3 "pnv-phb3"
OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3, PNV_PHB3)
/*
* PHB3 XICS Source for MSIs
@ -115,9 +116,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3RootBus, PNV_PHB3_ROOT_BUS)
/*
* PHB3 PCIe Host Bridge for PowerNV machines (POWER8)
*/
#define TYPE_PNV_PHB3 "pnv-phb3"
OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3, PNV_PHB3)
#define PNV_PHB3_NUM_M64 16
#define PNV_PHB3_NUM_REGS (0x1000 >> 3)
#define PNV_PHB3_NUM_LSI 8

8
include/hw/pci-host/pnv_phb4.h
View file

@ -17,8 +17,11 @@
#include "hw/ppc/xive.h"
#include "qom/object.h"
#define TYPE_PNV_PHB4 "pnv-phb4"
OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4)
typedef struct PnvPhb4PecStack PnvPhb4PecStack;
typedef struct PnvPHB4 PnvPHB4;
/*
* We have one such address space wrapper per possible device under
@ -59,9 +62,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4RootBus, PNV_PHB4_ROOT_BUS)
/*
* PHB4 PCIe Host Bridge for PowerNV machines (POWER9)
*/
#define TYPE_PNV_PHB4 "pnv-phb4"
OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4)
#define PNV_PHB4_MAX_LSIs 8
#define PNV_PHB4_MAX_INTs 4096
#define PNV_PHB4_MAX_MIST (PNV_PHB4_MAX_INTs >> 2)

7
include/hw/ppc/mac_dbdma.h
View file

@ -164,7 +164,9 @@ struct DBDMAState {
DBDMA_channel channels[DBDMA_CHANNELS];
QEMUBH *bh;
};
typedef struct DBDMAState DBDMAState;
#define TYPE_MAC_DBDMA "mac-dbdma"
OBJECT_DECLARE_SIMPLE_TYPE(DBDMAState, MAC_DBDMA)
/* Externally callable functions */
@ -173,7 +175,4 @@ void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
void *opaque);
void DBDMA_kick(DBDMAState *dbdma);
#define TYPE_MAC_DBDMA "mac-dbdma"
OBJECT_DECLARE_SIMPLE_TYPE(DBDMAState, MAC_DBDMA)
#endif

3
include/hw/qdev-core.h
View file

@ -725,7 +725,8 @@ void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n,
*
* Return: qemu_irq associated with GPIO or NULL if un-wired.
*/
qemu_irq qdev_get_gpio_out_connector(DeviceState *dev, const char *name, int n);
qemu_irq qdev_get_gpio_out_connector(const DeviceState *dev,
const char *name, int n);
/**
* qdev_intercept_gpio_out: Intercept an existing GPIO connection

18
include/hw/riscv/boot.h
View file

@ -43,18 +43,18 @@ bool riscv_is_32bit(RISCVHartArrayState *harts);
char *riscv_plic_hart_config_string(int hart_count);
void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts);
target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info,
target_ulong firmware_end_addr);
target_ulong riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
hwaddr *firmware_load_addr,
symbol_fn_t sym_cb);
hwaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,
hwaddr firmware_end_addr);
hwaddr riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
hwaddr *firmware_load_addr,
symbol_fn_t sym_cb);
const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
char *riscv_find_firmware(const char *firmware_filename,
const char *default_machine_firmware);
target_ulong riscv_load_firmware(const char *firmware_filename,
hwaddr *firmware_load_addr,
symbol_fn_t sym_cb);
hwaddr riscv_load_firmware(const char *firmware_filename,
hwaddr *firmware_load_addr,
symbol_fn_t sym_cb);
void riscv_load_kernel(MachineState *machine,
RISCVBootInfo *info,
target_ulong kernel_start_addr,

14
include/hw/riscv/boot_opensbi.h
View file

@ -29,17 +29,17 @@ enum sbi_scratch_options {
};
/** Representation dynamic info passed by previous booting stage */
struct fw_dynamic_info {
struct fw_dynamic_info64 {
/** Info magic */
target_long magic;
int64_t magic;
/** Info version */
target_long version;
int64_t version;
/** Next booting stage address */
target_long next_addr;
int64_t next_addr;
/** Next booting stage mode */
target_long next_mode;
int64_t next_mode;
/** Options for OpenSBI library */
target_long options;
int64_t options;
/**
* Preferred boot HART id
*
@ -55,7 +55,7 @@ struct fw_dynamic_info {
* stage can set it to -1UL which will force the FW_DYNAMIC firmware
* to use the relocation lottery mechanism.
*/
target_long boot_hart;
int64_t boot_hart;
};
/** Representation dynamic info passed by previous booting stage */

3
include/hw/riscv/iommu.h
View file

@ -24,18 +24,15 @@
#define TYPE_RISCV_IOMMU "riscv-iommu"
OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUState, RISCV_IOMMU)
typedef struct RISCVIOMMUState RISCVIOMMUState;
#define TYPE_RISCV_IOMMU_MEMORY_REGION "riscv-iommu-mr"
typedef struct RISCVIOMMUSpace RISCVIOMMUSpace;
#define TYPE_RISCV_IOMMU_PCI "riscv-iommu-pci"
OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI)
typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci;
#define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device"
OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS)
typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys;
#define FDT_IRQ_TYPE_EDGE_LOW 1

7
include/hw/scsi/scsi.h
View file

@ -10,7 +10,9 @@
#define MAX_SCSI_DEVS 255
typedef struct SCSIBus SCSIBus;
#define TYPE_SCSI_BUS "SCSI"
OBJECT_DECLARE_SIMPLE_TYPE(SCSIBus, SCSI_BUS)
typedef struct SCSIBusInfo SCSIBusInfo;
typedef struct SCSIDevice SCSIDevice;
typedef struct SCSIRequest SCSIRequest;
@ -151,9 +153,6 @@ struct SCSIBusInfo {
void (*drained_end)(SCSIBus *bus);
};
#define TYPE_SCSI_BUS "SCSI"
OBJECT_DECLARE_SIMPLE_TYPE(SCSIBus, SCSI_BUS)
struct SCSIBus {
BusState qbus;
int busnr;

10
include/hw/sysbus.h
View file

@ -70,17 +70,17 @@ struct SysBusDevice {
typedef void FindSysbusDeviceFunc(SysBusDevice *sbdev, void *opaque);
void sysbus_init_mmio(SysBusDevice *dev, MemoryRegion *memory);
MemoryRegion *sysbus_mmio_get_region(SysBusDevice *dev, int n);
MemoryRegion *sysbus_mmio_get_region(const SysBusDevice *dev, int n);
void sysbus_init_irq(SysBusDevice *dev, qemu_irq *p);
void sysbus_pass_irq(SysBusDevice *dev, SysBusDevice *target);
void sysbus_init_ioports(SysBusDevice *dev, uint32_t ioport, uint32_t size);
bool sysbus_has_irq(SysBusDevice *dev, int n);
bool sysbus_has_mmio(SysBusDevice *dev, unsigned int n);
bool sysbus_has_irq(const SysBusDevice *dev, int n);
bool sysbus_has_mmio(const SysBusDevice *dev, unsigned int n);
void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq);
bool sysbus_is_irq_connected(SysBusDevice *dev, int n);
qemu_irq sysbus_get_connected_irq(SysBusDevice *dev, int n);
bool sysbus_is_irq_connected(const SysBusDevice *dev, int n);
qemu_irq sysbus_get_connected_irq(const SysBusDevice *dev, int n);
void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr);
int sysbus_mmio_map_name(SysBusDevice *dev, const char*name, hwaddr addr);
void sysbus_mmio_map_overlap(SysBusDevice *dev, int n, hwaddr addr,

1
include/hw/uefi/var-service.h
View file

@ -9,6 +9,7 @@
#include "qemu/uuid.h"
#include "qemu/queue.h"
#include "system/memory.h"
#include "hw/uefi/var-service-edk2.h"
#define MAX_BUFFER_SIZE (64 * 1024)

5
include/hw/vfio/vfio-container-legacy.h
View file

@ -12,7 +12,8 @@
#include "hw/vfio/vfio-container.h"
#include "hw/vfio/vfio-cpr.h"
typedef struct VFIOLegacyContainer VFIOLegacyContainer;
OBJECT_DECLARE_SIMPLE_TYPE(VFIOLegacyContainer, VFIO_IOMMU_LEGACY);
typedef struct VFIODevice VFIODevice;
typedef struct VFIOGroup {
@ -35,6 +36,4 @@ struct VFIOLegacyContainer {
VFIOContainerCPR cpr;
};
OBJECT_DECLARE_SIMPLE_TYPE(VFIOLegacyContainer, VFIO_IOMMU_LEGACY);
#endif /* HW_VFIO_CONTAINER_LEGACY_H */

2
include/hw/virtio/virtio-net.h
View file

@ -202,7 +202,7 @@ struct VirtIONet {
uint8_t uni_overflow;
uint8_t *macs;
} mac_table;
uint32_t *vlans;
uint32_t vlans[MAX_VLAN];
virtio_net_conf net_conf;
NICConf nic_conf;
DeviceState *qdev;

5
include/hw/virtio/virtio-serial.h
View file

@ -29,7 +29,8 @@ struct virtio_serial_conf {
OBJECT_DECLARE_TYPE(VirtIOSerialPort, VirtIOSerialPortClass,
VIRTIO_SERIAL_PORT)
typedef struct VirtIOSerial VirtIOSerial;
#define TYPE_VIRTIO_SERIAL "virtio-serial-device"
OBJECT_DECLARE_SIMPLE_TYPE(VirtIOSerial, VIRTIO_SERIAL)
#define TYPE_VIRTIO_SERIAL_BUS "virtio-serial-bus"
OBJECT_DECLARE_SIMPLE_TYPE(VirtIOSerialBus, VIRTIO_SERIAL_BUS)
@ -221,7 +222,5 @@ size_t virtio_serial_guest_ready(VirtIOSerialPort *port);
*/
void virtio_serial_throttle_port(VirtIOSerialPort *port, bool throttle);
#define TYPE_VIRTIO_SERIAL "virtio-serial-device"
OBJECT_DECLARE_SIMPLE_TYPE(VirtIOSerial, VIRTIO_SERIAL)
#endif

9
include/migration/vmstate.h
View file

@ -727,15 +727,6 @@ extern const VMStateInfo vmstate_info_qlist;
.offset = offsetof(_state, _field), \
}
#define VMSTATE_BUFFER_POINTER_UNSAFE(_field, _state, _version, _size) { \
.name = (stringify(_field)), \
.version_id = (_version), \
.size = (_size), \
.info = &vmstate_info_buffer, \
.flags = VMS_BUFFER|VMS_POINTER, \
.offset = offsetof(_state, _field), \
}
/* Allocate a temporary of type 'tmp_type', set tmp->parent to _state
* and execute the vmsd on the temporary. Note that we're working with
* the whole of _state here, not a field within it.

7
include/net/can_emu.h
View file

@ -85,7 +85,9 @@ typedef struct qemu_can_filter {
#define QEMU_CAN_INV_FILTER 0x20000000U
typedef struct CanBusClientState CanBusClientState;
typedef struct CanBusState CanBusState;
#define TYPE_CAN_BUS "can-bus"
OBJECT_DECLARE_SIMPLE_TYPE(CanBusState, CAN_BUS)
typedef struct CanBusClientInfo {
bool (*can_receive)(CanBusClientState *);
@ -105,9 +107,6 @@ struct CanBusClientState {
bool fd_mode;
};
#define TYPE_CAN_BUS "can-bus"
OBJECT_DECLARE_SIMPLE_TYPE(CanBusState, CAN_BUS)
int can_bus_filter_match(struct qemu_can_filter *filter, qemu_canid_t can_id);
int can_bus_insert_client(CanBusState *bus, CanBusClientState *client);