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target/riscv: rvv: Modify minimum VLEN according to enabled vector extensions

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According to the RISC-V unprivileged specification, the VLEN should be greater
or equal to the ELEN. This commit modifies the minimum VLEN based on the vector
extensions and introduces a check rule for VLEN and ELEN.

  Extension     Minimum VLEN
* V                      128
* Zve64[d|f|x]            64
* Zve32[f|x]              32

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250923090729.1887406-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Max Chou 2025-09-23 17:07:29 +08:00 • committed by Alistair Francis
parent ae4a37f578
commit be50ff3a73
1 changed files with 17 additions and 2 deletions
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19
target/riscv/tcg/tcg-cpu.c
View file

@ -417,12 +417,21 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
Error **errp)
{
uint32_t min_vlen;
uint32_t vlen = cfg->vlenb << 3;
if (vlen > RV_VLEN_MAX || vlen < 128) {
if (riscv_has_ext(env, RVV)) {
min_vlen = 128;
} else if (cfg->ext_zve64x) {
min_vlen = 64;
} else if (cfg->ext_zve32x) {
min_vlen = 32;
}
if (vlen > RV_VLEN_MAX || vlen < min_vlen) {
error_setg(errp,
"Vector extension implementation only supports VLEN "
"in the range [128, %d]", RV_VLEN_MAX);
"in the range [%d, %d]", min_vlen, RV_VLEN_MAX);
return;
}
@ -432,6 +441,12 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
"in the range [8, 64]");
return;
}
if (vlen < cfg->elen) {
error_setg(errp, "Vector extension implementation requires VLEN "
"to be greater than or equal to ELEN");
return;
}
}
static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)