linux-user/aarch64: Clear TPIDR2_EL0 when delivering signals
linux-user/aarch64: Support TPIDR2_MAGIC signal frame record linux-user/aarch64: Support ZT_MAGIC signal frame record -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmiF1rwdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV935wf7BXGiD3m1MfLofofa w5/j4AjKw2sNAS3gVhmu9+BKKdctvNDxpNv4vx79j58iTuPCpi6roQ3vOEJWR0Vb 0UdJc/vNvFrXWLTW+W5nncKjCYZeTgSbWy3xwfnR3u4fk8YkUbGjVZ9TAgXl3dA1 NGagGqrlCqJpDYxbRWRIhXE+dF5zfNqU4gDTLG+C8xCN/gT7TkDIOU9sNb2uu1PC eI/SplpZYBDpdzpjko35peyq0tqUJrYT6P1MMjQckGpnKTSMynQmYvKVkloALRpW Zx3mBu9cWl77D57Fw4AijEiuUGhN0kZB12gH9VRp29rlTRr/MR4Y0seOU6XDc341 eGe5pg== =avvX -----END PGP SIGNATURE----- Merge tag 'pull-lu-20250726' of https://gitlab.com/rth7680/qemu into staging linux-user/aarch64: Clear TPIDR2_EL0 when delivering signals linux-user/aarch64: Support TPIDR2_MAGIC signal frame record linux-user/aarch64: Support ZT_MAGIC signal frame record # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmiF1rwdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV935wf7BXGiD3m1MfLofofa # w5/j4AjKw2sNAS3gVhmu9+BKKdctvNDxpNv4vx79j58iTuPCpi6roQ3vOEJWR0Vb # 0UdJc/vNvFrXWLTW+W5nncKjCYZeTgSbWy3xwfnR3u4fk8YkUbGjVZ9TAgXl3dA1 # NGagGqrlCqJpDYxbRWRIhXE+dF5zfNqU4gDTLG+C8xCN/gT7TkDIOU9sNb2uu1PC # eI/SplpZYBDpdzpjko35peyq0tqUJrYT6P1MMjQckGpnKTSMynQmYvKVkloALRpW # Zx3mBu9cWl77D57Fw4AijEiuUGhN0kZB12gH9VRp29rlTRr/MR4Y0seOU6XDc341 # eGe5pg== # =avvX # -----END PGP SIGNATURE----- # gpg: Signature made Sun 27 Jul 2025 03:35:24 EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-lu-20250726' of https://gitlab.com/rth7680/qemu: linux-user/aarch64: Support ZT_MAGIC signal frame record linux-user/aarch64: Support TPIDR2_MAGIC signal frame record linux-user/aarch64: Clear TPIDR2_EL0 when delivering signals Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
bf7da34454
1 changed files with 136 additions and 3 deletions
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@ -121,6 +121,30 @@ struct target_za_context {
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#define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \
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TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES)
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#define TARGET_TPIDR2_MAGIC 0x54504902
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struct target_tpidr2_context {
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struct target_aarch64_ctx head;
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uint64_t tpidr2;
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};
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#define TARGET_ZT_MAGIC 0x5a544e01
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struct target_zt_context {
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struct target_aarch64_ctx head;
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uint16_t nregs;
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uint16_t reserved[3];
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/* ZTn register data immediately follows */
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};
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#define TARGET_ZT_SIG_REG_BYTES (512 / 8)
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#define TARGET_ZT_SIG_REGS_SIZE(n) (TARGET_ZT_SIG_REG_BYTES * (n))
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#define TARGET_ZT_SIG_CONTEXT_SIZE(n) (sizeof(struct target_zt_context) + \
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TARGET_ZT_SIG_REGS_SIZE(n))
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#define TARGET_ZT_SIG_REGS_OFFSET sizeof(struct target_zt_context)
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QEMU_BUILD_BUG_ON(TARGET_ZT_SIG_REG_BYTES != \
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sizeof_field(CPUARMState, za_state.zt0));
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struct target_rt_sigframe {
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struct target_siginfo info;
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struct target_ucontext uc;
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@ -253,6 +277,36 @@ static void target_setup_za_record(struct target_za_context *za,
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}
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}
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static void target_setup_tpidr2_record(struct target_tpidr2_context *tpidr2,
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CPUARMState *env)
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{
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__put_user(TARGET_TPIDR2_MAGIC, &tpidr2->head.magic);
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__put_user(sizeof(struct target_tpidr2_context), &tpidr2->head.size);
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__put_user(env->cp15.tpidr2_el0, &tpidr2->tpidr2);
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}
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static void target_setup_zt_record(struct target_zt_context *zt,
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CPUARMState *env, int size)
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{
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uint64_t *z;
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memset(zt, 0, sizeof(*zt));
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__put_user(TARGET_ZT_MAGIC, &zt->head.magic);
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__put_user(size, &zt->head.size);
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/*
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* The record format allows for multiple ZT regs, but
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* currently there is only one, ZT0.
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*/
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__put_user(1, &zt->nregs);
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assert(size == TARGET_ZT_SIG_CONTEXT_SIZE(1));
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/* ZT0 is the same byte-stream format as SVE regs and ZA */
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z = (void *)zt + TARGET_ZT_SIG_REGS_OFFSET;
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for (int i = 0; i < ARRAY_SIZE(env->za_state.zt0); i++) {
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__put_user_e(env->za_state.zt0[i], z + i, le);
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}
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}
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static void target_restore_general_frame(CPUARMState *env,
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struct target_rt_sigframe *sf)
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{
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@ -403,6 +457,36 @@ static bool target_restore_za_record(CPUARMState *env,
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return true;
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}
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static void target_restore_tpidr2_record(CPUARMState *env,
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struct target_tpidr2_context *tpidr2)
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{
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__get_user(env->cp15.tpidr2_el0, &tpidr2->tpidr2);
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}
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static bool target_restore_zt_record(CPUARMState *env,
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struct target_zt_context *zt, int size,
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int svcr)
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{
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uint16_t nregs;
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uint64_t *z;
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if (!(FIELD_EX64(svcr, SVCR, ZA))) {
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return false;
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}
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__get_user(nregs, &zt->nregs);
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if (nregs != 1) {
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return false;
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}
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z = (void *)zt + TARGET_ZT_SIG_REGS_OFFSET;
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for (int i = 0; i < ARRAY_SIZE(env->za_state.zt0); i++) {
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__get_user_e(env->za_state.zt0[i], z + i, le);
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}
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return true;
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}
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static int target_restore_sigframe(CPUARMState *env,
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struct target_rt_sigframe *sf)
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{
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@ -410,10 +494,13 @@ static int target_restore_sigframe(CPUARMState *env,
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struct target_fpsimd_context *fpsimd = NULL;
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struct target_sve_context *sve = NULL;
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struct target_za_context *za = NULL;
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struct target_tpidr2_context *tpidr2 = NULL;
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struct target_zt_context *zt = NULL;
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uint64_t extra_datap = 0;
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bool used_extra = false;
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int sve_size = 0;
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int za_size = 0;
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int zt_size = 0;
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int svcr = 0;
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target_restore_general_frame(env, sf);
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@ -460,6 +547,23 @@ static int target_restore_sigframe(CPUARMState *env,
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za_size = size;
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break;
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case TARGET_TPIDR2_MAGIC:
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if (tpidr2 || size != sizeof(struct target_tpidr2_context) ||
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!cpu_isar_feature(aa64_sme, env_archcpu(env))) {
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goto err;
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}
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tpidr2 = (struct target_tpidr2_context *)ctx;
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break;
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case TARGET_ZT_MAGIC:
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if (zt || size != TARGET_ZT_SIG_CONTEXT_SIZE(1) ||
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!cpu_isar_feature(aa64_sme2, env_archcpu(env))) {
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goto err;
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}
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zt = (struct target_zt_context *)ctx;
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zt_size = size;
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break;
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case TARGET_EXTRA_MAGIC:
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if (extra || size != sizeof(struct target_extra_context)) {
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goto err;
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@ -497,6 +601,16 @@ static int target_restore_sigframe(CPUARMState *env,
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if (za && !target_restore_za_record(env, za, za_size, &svcr)) {
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goto err;
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}
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if (tpidr2) {
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target_restore_tpidr2_record(env, tpidr2);
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}
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/*
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* NB that we must restore ZT after ZA so the check that there's
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* no ZT record if SVCR.ZA is 0 gets the right value of SVCR.
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*/
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if (zt && !target_restore_zt_record(env, zt, zt_size, svcr)) {
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goto err;
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}
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if (env->svcr != svcr) {
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env->svcr = svcr;
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arm_rebuild_hflags(env);
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@ -568,8 +682,9 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
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.total_size = offsetof(struct target_rt_sigframe,
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uc.tuc_mcontext.__reserved),
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};
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int fpsimd_ofs, fr_ofs, sve_ofs = 0, za_ofs = 0;
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int sve_size = 0, za_size = 0;
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int fpsimd_ofs, fr_ofs, sve_ofs = 0, za_ofs = 0, tpidr2_ofs = 0;
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int zt_ofs = 0;
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int sve_size = 0, za_size = 0, tpidr2_size = 0, zt_size = 0;
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struct target_rt_sigframe *frame;
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struct target_rt_frame_record *fr;
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abi_ulong frame_addr, return_addr;
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@ -585,6 +700,8 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
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sve_ofs = alloc_sigframe_space(sve_size, &layout);
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}
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if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
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tpidr2_size = sizeof(struct target_tpidr2_context);
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tpidr2_ofs = alloc_sigframe_space(tpidr2_size, &layout);
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/* ZA state needs saving only if it is enabled. */
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if (FIELD_EX64(env->svcr, SVCR, ZA)) {
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za_size = TARGET_ZA_SIG_CONTEXT_SIZE(sme_vq(env));
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@ -593,6 +710,12 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
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}
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za_ofs = alloc_sigframe_space(za_size, &layout);
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}
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if (cpu_isar_feature(aa64_sme2, env_archcpu(env)) &&
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FIELD_EX64(env->svcr, SVCR, ZA)) {
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/* If SME ZA storage is enabled, we must also save SME2 ZT0 */
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zt_size = TARGET_ZT_SIG_CONTEXT_SIZE(1);
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zt_ofs = alloc_sigframe_space(zt_size, &layout);
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}
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if (layout.extra_ofs) {
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/* Reserve space for the extra end marker. The standard end marker
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@ -644,6 +767,12 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
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if (za_ofs) {
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target_setup_za_record((void *)frame + za_ofs, env, za_size);
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}
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if (tpidr2_ofs) {
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target_setup_tpidr2_record((void *)frame + tpidr2_ofs, env);
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}
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if (zt_ofs) {
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target_setup_zt_record((void *)frame + zt_ofs, env, zt_size);
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}
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/* Set up the stack frame for unwinding. */
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fr = (void *)frame + fr_ofs;
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@ -666,8 +795,12 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
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env->btype = 2;
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}
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/* Invoke the signal handler with both SM and ZA disabled. */
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/*
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* Invoke the signal handler with a clean SME state: both SM and ZA
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* disabled and TPIDR2_EL0 cleared.
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*/
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aarch64_set_svcr(env, 0, R_SVCR_SM_MASK | R_SVCR_ZA_MASK);
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env->cp15.tpidr2_el0 = 0;
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if (info) {
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frame->info = *info;
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