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pnv/xive2: Support ESB Escalation

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Add support for XIVE ESB Interrupt Escalation.

Suggested-by: Michael Kowal <kowal@linux.ibm.com>
[This change was taken from a patch provided by Michael Kowal.]
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com>
Tested-by: Gautam Menghani <gautam@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-18-npiggin@gmail.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Glenn Miles 2025-05-12 13:10:26 +10:00 • committed by Cédric Le Goater
parent 279031bc03
commit c2cee7477f
3 changed files with 59 additions and 17 deletions
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62
hw/intc/xive2.c
View file

@ -1552,18 +1552,39 @@ do_escalation:
}
}
/*
* The END trigger becomes an Escalation trigger
*/
xive2_router_end_notify(xrtr,
xive_get_field32(END2_W4_END_BLOCK, end.w4),
xive_get_field32(END2_W4_ESC_END_INDEX, end.w4),
xive_get_field32(END2_W5_ESC_END_DATA, end.w5));
if (xive2_end_is_escalate_end(&end)) {
/*
* Perform END Adaptive escalation processing
* The END trigger becomes an Escalation trigger
*/
xive2_router_end_notify(xrtr,
xive_get_field32(END2_W4_END_BLOCK, end.w4),
xive_get_field32(END2_W4_ESC_END_INDEX, end.w4),
xive_get_field32(END2_W5_ESC_END_DATA, end.w5));
} /* end END adaptive escalation */
else {
uint32_t lisn; /* Logical Interrupt Source Number */
/*
* Perform ESB escalation processing
* E[N] == 1 --> N
* Req[Block] <- E[ESB_Block]
* Req[Index] <- E[ESB_Index]
* Req[Offset] <- 0x000
* Execute <ESB Store> Req command
*/
lisn = XIVE_EAS(xive_get_field32(END2_W4_END_BLOCK, end.w4),
xive_get_field32(END2_W4_ESC_END_INDEX, end.w4));
xive2_notify(xrtr, lisn, true /* pq_checked */);
}
return;
}
void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked)
void xive2_notify(Xive2Router *xrtr , uint32_t lisn, bool pq_checked)
{
Xive2Router *xrtr = XIVE2_ROUTER(xn);
uint8_t eas_blk = XIVE_EAS_BLOCK(lisn);
uint32_t eas_idx = XIVE_EAS_INDEX(lisn);
Xive2Eas eas;
@ -1606,13 +1627,30 @@ void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked)
return;
}
/* TODO: add support for EAS resume */
if (xive2_eas_is_resume(&eas)) {
qemu_log_mask(LOG_UNIMP,
"XIVE: EAS resume processing unimplemented - LISN %x\n",
lisn);
return;
}
/*
* The event trigger becomes an END trigger
*/
xive2_router_end_notify(xrtr,
xive_get_field64(EAS2_END_BLOCK, eas.w),
xive_get_field64(EAS2_END_INDEX, eas.w),
xive_get_field64(EAS2_END_DATA, eas.w));
xive_get_field64(EAS2_END_BLOCK, eas.w),
xive_get_field64(EAS2_END_INDEX, eas.w),
xive_get_field64(EAS2_END_DATA, eas.w));
return;
}
void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked)
{
Xive2Router *xrtr = XIVE2_ROUTER(xn);
xive2_notify(xrtr, lisn, pq_checked);
return;
}
static const Property xive2_router_properties[] = {

1
include/hw/ppc/xive2.h
View file

@ -80,6 +80,7 @@ int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd,
uint32_t xive2_router_get_config(Xive2Router *xrtr);
void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked);
void xive2_notify(Xive2Router *xrtr, uint32_t lisn, bool pq_checked);
/*
* XIVE2 Presenter (POWER10)

13
include/hw/ppc/xive2_regs.h
View file

@ -39,15 +39,18 @@
typedef struct Xive2Eas {
uint64_t w;
#define EAS2_VALID PPC_BIT(0)
#define EAS2_END_BLOCK PPC_BITMASK(4, 7) /* Destination EQ block# */
#define EAS2_END_INDEX PPC_BITMASK(8, 31) /* Destination EQ index */
#define EAS2_MASKED PPC_BIT(32) /* Masked */
#define EAS2_END_DATA PPC_BITMASK(33, 63) /* written to the EQ */
#define EAS2_VALID PPC_BIT(0)
#define EAS2_QOS PPC_BIT(1, 2) /* Quality of Service(unimp) */
#define EAS2_RESUME PPC_BIT(3) /* END Resume(unimp) */
#define EAS2_END_BLOCK PPC_BITMASK(4, 7) /* Destination EQ block# */
#define EAS2_END_INDEX PPC_BITMASK(8, 31) /* Destination EQ index */
#define EAS2_MASKED PPC_BIT(32) /* Masked */
#define EAS2_END_DATA PPC_BITMASK(33, 63) /* written to the EQ */
} Xive2Eas;
#define xive2_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS2_VALID)
#define xive2_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS2_MASKED)
#define xive2_eas_is_resume(eas) (be64_to_cpu((eas)->w) & EAS2_RESUME)
void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf);