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target/arm: Correct condition of aa64_atomics feature function

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The ARMv8.1-Atomics feature (renamed FEAT_LSE in more modern versions
of the Arm ARM) has always ben indicated by ID_AA64ISAR0.ATOMIC being
0b0010 or greater; 0b0001 is a reserved unused value.

We were incorrectly checking for != 0; this had no harmful effects
because all the CPUs set their value for this field to either 0
(for not having the feature) or 2 (if they do have it), but it's
better to match what the architecture specifies here.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250819145659.2165160-1-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2025-08-19 15:56:58 +01:00
parent e0ca100425
commit c2fae59709
1 changed files with 1 additions and 1 deletions
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2
target/arm/cpu-features.h
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@ -408,7 +408,7 @@ static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
{
return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) != 0;
return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) >= 2;
}
static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)