wip! untested: rust uart

hw/char/Kconfig

@@ -95,3 +95,8 @@ config IP_OCTAL_232
     bool
     default y
     depends on IPACK
+
+config DIALOG_UART
+    bool
+    depends on HAVE_RUST
+    select X_DIALOG_UART_RUST

hw/cr16c/Kconfig

@@ -1,6 +1,8 @@
 config VIRT
     bool
     select UNIMP
+    select DIALOG_UART
 
 config DE410
     bool
+    select DIALOG_UART

rust/Cargo.lock

@@ -1,6 +1,6 @@
 # This file is automatically @generated by Cargo.
 # It is not intended for manual editing.
-version = 3
+version = 4
 
 [[package]]
 name = "anyhow"
@@ -91,6 +91,25 @@ dependencies = [
  "qemu_macros",
 ]
 
+[[package]]
+name = "dialog_uart"
+version = "0.1.0"
+dependencies = [
+ "bilge",
+ "bilge-impl",
+ "bits",
+ "bql",
+ "chardev",
+ "common",
+ "glib-sys",
+ "hwcore",
+ "migration",
+ "qom",
+ "system",
+ "trace",
+ "util",
+]
+
 [[package]]
 name = "either"
 version = "1.12.0"

rust/Cargo.toml

@@ -2,6 +2,7 @@
 resolver = "2"
 members = [
     "hw/char/pl011",
+    "hw/char/dialog_uart",
     "hw/timer/hpet",
     "tests",
 ]

rust/hw/char/Kconfig

@@ -1,2 +1,5 @@
 config X_PL011_RUST
     bool
+
+config X_DIALOG_UART_RUST
+    bool

rust/hw/char/dialog_uart/Cargo.toml

@@ -0,0 +1,31 @@
+[package]
+name = "dialog_uart"
+version = "0.1.0"
+authors = ["fridtjof <fridtjof@das-labor.org>", "Manos Pitsidianakis <manos.pitsidianakis@linaro.org>"]
+description = "dialog_uart device model for QEMU"
+resolver = "2"
+publish = false
+
+edition.workspace = true
+homepage.workspace = true
+license.workspace = true
+repository.workspace = true
+rust-version.workspace = true
+
+[dependencies]
+glib-sys.workspace = true
+bilge = { version = "0.2.0" }
+bilge-impl = { version = "0.2.0" }
+bits = { path = "../../../bits" }
+common = { path = "../../../common" }
+util = { path = "../../../util" }
+bql = { path = "../../../bql" }
+migration = { path = "../../../migration" }
+qom = { path = "../../../qom" }
+chardev = { path = "../../../chardev" }
+system = { path = "../../../system" }
+hwcore = { path = "../../../hw/core" }
+trace = { path = "../../../trace" }
+
+[lints]
+workspace = true

rust/hw/char/dialog_uart/build.rs

@@ -0,0 +1 @@
+../../../util/build.rs

rust/hw/char/dialog_uart/meson.build

@@ -0,0 +1,51 @@
+# TODO: Remove this comment when the clang/libclang mismatch issue is solved.
+#
+# Rust bindings generation with `bindgen` might fail in some cases where the
+# detected `libclang` does not match the expected `clang` version/target. In
+# this case you must pass the path to `clang` and `libclang` to your build
+# command invocation using the environment variables CLANG_PATH and
+# LIBCLANG_PATH
+_libdialog_uart_bindings_inc_rs = rust.bindgen(
+    input: 'wrapper.h',
+    dependencies: common_ss.all_dependencies(),
+    output: 'bindings.inc.rs',
+    include_directories: bindings_incdir,
+    bindgen_version: ['>=0.60.0'],
+    args: bindgen_args_common,
+    c_args: bindgen_c_args,
+)
+
+_libdialog_uart_rs = static_library(
+  'dialog_uart',
+  structured_sources(
+      [
+          'src/lib.rs',
+          'src/bindings.rs',
+          'src/device.rs',
+          'src/registers.rs',
+      ],
+      {'.' : _libdialog_uart_bindings_inc_rs},
+  ),
+  override_options: ['rust_std=2021', 'build.rust_std=2021'],
+  rust_abi: 'rust',
+  dependencies: [
+    bilge_rs,
+    bilge_impl_rs,
+    bits_rs,
+    common_rs,
+    glib_sys_rs,
+    util_rs,
+    migration_rs,
+    bql_rs,
+    qom_rs,
+    chardev_rs,
+    system_rs,
+    hwcore_rs,
+    trace_rs
+  ],
+)
+
+rust_devices_ss.add(when: 'CONFIG_X_DIALOG_UART_RUST', if_true: [declare_dependency(
+  link_whole: [_libdialog_uart_rs],
+  variables: {'crate': 'dialog_uart'},
+)])

rust/hw/char/dialog_uart/src/bindings.rs

@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+#![allow(
+    dead_code,
+    improper_ctypes_definitions,
+    improper_ctypes,
+    non_camel_case_types,
+    non_snake_case,
+    non_upper_case_globals,
+    unnecessary_transmutes,
+    unsafe_op_in_unsafe_fn,
+    clippy::pedantic,
+    clippy::restriction,
+    clippy::style,
+    clippy::missing_const_for_fn,
+    clippy::ptr_offset_with_cast,
+    clippy::useless_transmute,
+    clippy::missing_safety_doc,
+    clippy::too_many_arguments
+)]
+
+//! `bindgen`-generated declarations.
+
+use glib_sys::{
+    gboolean, guint, GArray, GByteArray, GHashTable, GHashTableIter, GIOCondition, GList,
+    GMainContext, GPollFD, GPtrArray, GSList, GSource, GSourceFunc, GString,
+};
+
+#[cfg(MESON)]
+include!("bindings.inc.rs");
+
+#[cfg(not(MESON))]
+include!(concat!(env!("OUT_DIR"), "/bindings.inc.rs"));

rust/hw/char/dialog_uart/src/device.rs

@@ -0,0 +1,505 @@
+// Copyright 2024, Linaro Limited
+// Copyright 2026, fridtjof
+// Author(s): Manos Pitsidianakis <manos.pitsidianakis@linaro.org>, fridtjof <fridtjof@das-labor.org>
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+use std::{ffi::CStr};
+
+use bql::BqlRefCell;
+use chardev::{CharFrontend, Chardev, Event};
+use common::uninit_field_mut;
+use hwcore::{
+    Clock, ClockEvent, DeviceImpl, DeviceMethods, DeviceState, IRQState, InterruptSource,
+    ResetType, ResettablePhasesImpl, SysBusDevice, SysBusDeviceImpl, SysBusDeviceMethods,
+};
+use migration::{
+    impl_vmstate_forward, impl_vmstate_struct, vmstate_fields, vmstate_of,
+    vmstate_subsections, vmstate_unused, VMStateDescription, VMStateDescriptionBuilder,
+};
+use qom::{prelude::*, ObjectImpl, Owned, ParentField, ParentInit};
+use system::{hwaddr, MemoryRegion, MemoryRegionOps, MemoryRegionOpsBuilder};
+use util::{log::Log, log_mask_ln, ResultExt};
+
+use crate::registers::{self, Interrupt, RegisterOffset};
+
+// TODO: You must disable the UART before any of the control registers are
+// reprogrammed. When the UART is disabled in the middle of transmission or
+// reception, it completes the current character before stopping
+
+/// QEMU sourced constant.
+pub const PL011_FIFO_DEPTH: u32 = 16;
+
+// FIFOs use 32-bit indices instead of usize, for compatibility with
+// the migration stream produced by the C version of this device.
+#[repr(transparent)]
+#[derive(Debug, Default)]
+pub struct Fifo([registers::Data; PL011_FIFO_DEPTH as usize]);
+impl_vmstate_forward!(Fifo);
+
+impl Fifo {
+    const fn len(&self) -> u32 {
+        self.0.len() as u32
+    }
+}
+
+impl std::ops::IndexMut<u32> for Fifo {
+    fn index_mut(&mut self, idx: u32) -> &mut Self::Output {
+        &mut self.0[idx as usize]
+    }
+}
+
+impl std::ops::Index<u32> for Fifo {
+    type Output = registers::Data;
+
+    fn index(&self, idx: u32) -> &Self::Output {
+        &self.0[idx as usize]
+    }
+}
+
+#[repr(C)]
+#[derive(Debug, Default)]
+pub struct SC144UartRegisters {
+    #[doc(alias = "ctrl")]
+    pub control: registers::Control,
+    pub dmacr: u32,
+    pub int_enabled: Interrupt,
+    pub int_level: Interrupt,
+    pub read_fifo: Fifo,
+    pub ilpr: u32,
+    pub ifl: u32,
+    pub read_pos: u32,
+    pub read_count: u32,
+    pub read_trigger: u32,
+}
+
+#[repr(C)]
+#[derive(qom::Object, hwcore::Device)]
+/// PL011 Device Model in QEMU
+pub struct SC144UartState {
+    pub parent_obj: ParentField<SysBusDevice>,
+    pub iomem: MemoryRegion,
+    #[doc(alias = "chr")]
+    #[property(rename = "chardev")]
+    pub char_backend: CharFrontend,
+    pub regs: BqlRefCell<SC144UartRegisters>,
+    /// QEMU interrupts
+    ///
+    /// ```text
+    ///  * sysbus MMIO region 0: device registers
+    ///  * sysbus IRQ 0: `UARTINTR` (combined interrupt line)
+    ///  * sysbus IRQ 1: `UARTRXINTR` (receive FIFO interrupt line)
+    ///  * sysbus IRQ 2: `UARTTXINTR` (transmit FIFO interrupt line)
+    ///  * sysbus IRQ 3: `UARTRTINTR` (receive timeout interrupt line)
+    ///  * sysbus IRQ 4: `UARTMSINTR` (momem status interrupt line)
+    ///  * sysbus IRQ 5: `UARTEINTR` (error interrupt line)
+    /// ```
+    #[doc(alias = "irq")]
+    pub interrupts: [InterruptSource; IRQMASK.len()],
+    #[doc(alias = "clk")]
+    pub clock: Owned<Clock>,
+    #[doc(alias = "migrate_clk")]
+    #[property(rename = "migrate-clk", default = true)]
+    pub migrate_clock: bool,
+}
+
+qom_isa!(SC144UartState : SysBusDevice, DeviceState, Object);
+
+#[repr(C)]
+pub struct SC144UartClass {
+    parent_class: <SysBusDevice as ObjectType>::Class,
+}
+
+trait PL011Impl: SysBusDeviceImpl + IsA<SC144UartState> {}
+
+impl SC144UartClass {
+    fn class_init<T: PL011Impl>(&mut self) {
+        self.parent_class.class_init::<T>();
+    }
+}
+
+unsafe impl ObjectType for SC144UartState {
+    type Class = SC144UartClass;
+    const TYPE_NAME: &'static CStr = crate::TYPE_SC144UART;
+}
+
+impl PL011Impl for SC144UartState {}
+
+impl ObjectImpl for SC144UartState {
+    type ParentType = SysBusDevice;
+
+    const INSTANCE_INIT: Option<unsafe fn(ParentInit<Self>)> = Some(Self::init);
+    const INSTANCE_POST_INIT: Option<fn(&Self)> = Some(Self::post_init);
+    const CLASS_INIT: fn(&mut Self::Class) = Self::Class::class_init::<Self>;
+}
+
+impl DeviceImpl for SC144UartState {
+    const VMSTATE: Option<VMStateDescription<Self>> = Some(VMSTATE_SC144UART);
+    const REALIZE: Option<fn(&Self) -> util::Result<()>> = Some(Self::realize);
+}
+
+impl ResettablePhasesImpl for SC144UartState {
+    const HOLD: Option<fn(&Self, ResetType)> = Some(Self::reset_hold);
+}
+
+impl SysBusDeviceImpl for SC144UartState {}
+
+impl SC144UartRegisters {
+    pub(self) fn read(&mut self, offset: RegisterOffset) -> (bool, u16) {
+        use RegisterOffset::*;
+
+        let mut update_irq = false;
+        let result = match offset {
+            CTRL => u16::from(self.control).into(),
+            RXTX => self.read_data_register(&mut update_irq),
+            CLEAR_TX_INT | CLEAR_RX_INT => 0,
+            ERROR => 0, // TODO par_status, dma_parity_error
+        };
+        (update_irq, result)
+    }
+
+    pub(self) fn write(
+        &mut self,
+        offset: RegisterOffset,
+        value: u16,
+        _char_frontend: &CharFrontend,
+    ) -> bool {
+        eprintln!("write offset {offset:?} value {value}");
+        use RegisterOffset::*;
+        match offset {
+            RXTX => return self.write_data_register(value),
+            CTRL => {
+                // ??? Need to implement the enable bit.
+                self.control = value.into();
+            },
+            CLEAR_TX_INT | CLEAR_RX_INT => todo!(),
+            ERROR => todo!()
+        }
+        false
+    }
+
+    fn read_data_register(&mut self, update: &mut bool) -> u16 {
+        let c = self.read_fifo[self.read_pos];
+
+        if self.read_count > 0 {
+            self.read_count -= 1;
+            self.read_pos = (self.read_pos + 1) & (self.fifo_depth() - 1);
+        }
+        if self.read_count == 0 {
+        }
+        if self.read_count + 1 == self.read_trigger {
+            self.int_level &= !Interrupt::RX;
+        }
+        *update = true;
+        u16::from(c)
+    }
+
+    fn write_data_register(&mut self, value: u16) -> bool {
+        if !self.control.enable_transmit() {
+            log_mask_ln!(Log::GuestError, " SC144 UART data written to disabled TX UART");
+        }
+        // interrupts always checked
+        let _ = false && self.fifo_rx_put(value.into());
+        self.int_level |= Interrupt::TX;
+        true
+    }
+
+    pub fn reset(&mut self) {
+        self.dmacr = 0;
+        self.int_enabled = 0.into();
+        self.int_level = 0.into();
+        self.ilpr = 0;
+        self.read_trigger = 1;
+        self.ifl = 0x12;
+        self.control.reset();
+        self.reset_rx_fifo();
+        self.reset_tx_fifo();
+    }
+
+    pub fn reset_rx_fifo(&mut self) {
+        self.read_count = 0;
+        self.read_pos = 0;
+    }
+
+    pub fn reset_tx_fifo(&mut self) {}
+
+    #[inline]
+    pub fn fifo_enabled(&self) -> bool {
+        false
+    }
+
+    #[inline]
+    pub fn fifo_depth(&self) -> u32 {
+        1
+    }
+
+    #[must_use]
+    pub fn fifo_rx_put(&mut self, value: registers::Data) -> bool {
+        let depth = self.fifo_depth();
+        assert!(depth > 0);
+        let slot = (self.read_pos + self.read_count) & (depth - 1);
+        self.read_fifo[slot] = value;
+        self.read_count += 1;
+        if self.read_count == depth {}
+
+        if self.read_count == self.read_trigger {
+            self.int_level |= Interrupt::RX;
+            return true;
+        }
+        false
+    }
+
+    pub fn post_load(&mut self) -> Result<(), migration::InvalidError> {
+        /* Sanity-check input state */
+        if self.read_pos >= self.read_fifo.len() || self.read_count > self.read_fifo.len() {
+            return Err(migration::InvalidError);
+        }
+
+        if !self.fifo_enabled() && self.read_count > 0 && self.read_pos > 0 {
+            // Older versions of PL011 didn't ensure that the single
+            // character in the FIFO in FIFO-disabled mode is in
+            // element 0 of the array; convert to follow the current
+            // code's assumptions.
+            self.read_fifo[0] = self.read_fifo[self.read_pos];
+            self.read_pos = 0;
+        }
+
+        Ok(())
+    }
+}
+
+impl SC144UartState {
+    /// Initializes a pre-allocated, uninitialized instance of `SC144UartState`.
+    ///
+    /// # Safety
+    ///
+    /// `self` must point to a correctly sized and aligned location for the
+    /// `SC144UartState` type. It must not be called more than once on the same
+    /// location/instance. All its fields are expected to hold uninitialized
+    /// values with the sole exception of `parent_obj`.
+    unsafe fn init(mut this: ParentInit<Self>) {
+        static PL011_OPS: MemoryRegionOps<SC144UartState> = MemoryRegionOpsBuilder::<SC144UartState>::new()
+            .read(&SC144UartState::read)
+            .write(&SC144UartState::write)
+            .native_endian()
+            .impl_sizes(2, 2)
+            .build();
+
+        // SAFETY: this and this.iomem are guaranteed to be valid at this point
+        MemoryRegion::init_io(
+            &mut uninit_field_mut!(*this, iomem),
+            &PL011_OPS,
+            "sc144uart",
+            10,
+        );
+
+        uninit_field_mut!(*this, regs).write(Default::default());
+
+        let clock = DeviceState::init_clock_in(
+            &mut this,
+            "clk",
+            &Self::clock_update,
+            ClockEvent::ClockUpdate,
+        );
+        uninit_field_mut!(*this, clock).write(clock);
+    }
+
+    const fn clock_update(&self, _event: ClockEvent) {
+        /* pl011_trace_baudrate_change(s); */
+    }
+
+    pub fn clock_needed(&self) -> bool {
+        self.migrate_clock
+    }
+
+    fn post_init(&self) {
+        self.init_mmio(&self.iomem);
+        for irq in self.interrupts.iter() {
+            self.init_irq(irq);
+        }
+    }
+
+    fn read(&self, offset: hwaddr, _size: u32) -> u64 {
+        match RegisterOffset::try_from(offset) {
+            Err(_) => {
+                log_mask_ln!(Log::GuestError, "SC144UartState::read: Bad offset {offset}");
+                0
+            }
+            Ok(field) => {
+                let (update_irq, result) = self.regs.borrow_mut().read(field);
+                if update_irq {
+                    self.update();
+                    self.char_backend.accept_input();
+                }
+                result.into()
+            }
+        }
+    }
+
+    fn write(&self, offset: hwaddr, value: u64, _size: u32) {
+        let mut update_irq = false;
+        if let Ok(field) = RegisterOffset::try_from(offset) {
+            // qemu_chr_fe_write_all() calls into the can_receive
+            // callback, so handle writes before entering PL011Registers.
+            if field == RegisterOffset::RXTX {
+                // ??? Check if transmitter is enabled.
+                let ch: [u8; 1] = [value as u8];
+                // XXX this blocks entire thread. Rewrite to use
+                // qemu_chr_fe_write and background I/O callbacks
+                let _ = self.char_backend.write_all(&ch);
+            }
+
+            update_irq = self
+                .regs
+                .borrow_mut()
+                .write(field, value as u16, &self.char_backend);
+        } else {
+            log_mask_ln!(
+                Log::GuestError,
+                "SC144UartState::write: Bad offset {offset} value {value}"
+            );
+        }
+        if update_irq {
+            self.update();
+        }
+    }
+
+    fn can_receive(&self) -> u32 {
+        let regs = self.regs.borrow();
+        // trace_pl011_can_receive(s->lcr, s->read_count, r);
+        regs.fifo_depth() - regs.read_count
+    }
+
+    fn receive(&self, buf: &[u8]) {
+        let mut regs = self.regs.borrow_mut();
+
+        let mut update_irq = false;
+        for &c in buf {
+            let c: u16 = c.into();
+            update_irq |= regs.fifo_rx_put(c.into());
+        }
+
+        // Release the BqlRefCell before calling self.update()
+        drop(regs);
+        if update_irq {
+            self.update();
+        }
+    }
+
+    fn event(&self, _event: Event) {
+        let update_irq = false;
+        let regs = self.regs.borrow_mut();
+        // Release the BqlRefCell before calling self.update()
+        drop(regs);
+
+        if update_irq {
+            self.update()
+        }
+    }
+
+    fn realize(&self) -> util::Result<()> {
+        self.char_backend
+            .enable_handlers(self, Self::can_receive, Self::receive, Self::event);
+        Ok(())
+    }
+
+    fn reset_hold(&self, _type: ResetType) {
+        self.regs.borrow_mut().reset();
+    }
+
+    fn update(&self) {
+        let regs = self.regs.borrow();
+        let flags = regs.int_level & regs.int_enabled;
+        for (irq, i) in self.interrupts.iter().zip(IRQMASK) {
+            irq.set(flags.any_set(i));
+        }
+    }
+
+    pub fn post_load(&self, _version_id: u8) -> Result<(), migration::InvalidError> {
+        self.regs.borrow_mut().post_load()
+    }
+}
+
+/// Which bits in the interrupt status matter for each outbound IRQ line ?
+const IRQMASK: [Interrupt; 6] = [
+    Interrupt::all(),
+    Interrupt::RX,
+    Interrupt::TX,
+    Interrupt::RT,
+    Interrupt::MS,
+    Interrupt::E,
+];
+
+/// # Safety
+///
+/// We expect the FFI user of this function to pass a valid pointer for `chr`
+/// and `irq`.
+#[no_mangle]
+pub unsafe extern "C" fn sc144uart_create(
+    addr: u64,
+    irq: *mut IRQState,
+    chr: *mut Chardev,
+) -> *mut DeviceState {
+    // SAFETY: The callers promise that they have owned references.
+    // They do not gift them to sc144uart_create, so use `Owned::from`.
+    let irq = unsafe { Owned::<IRQState>::from(&*irq) };
+
+    let dev = SC144UartState::new();
+    if !chr.is_null() {
+        let chr = unsafe { Owned::<Chardev>::from(&*chr) };
+        dev.prop_set_chr("chardev", &chr);
+    }
+    dev.sysbus_realize().unwrap_fatal();
+    dev.mmio_map(0, addr);
+    dev.connect_irq(0, &irq);
+
+    // The pointer is kept alive by the QOM tree; drop the owned ref
+    dev.as_mut_ptr()
+}
+
+/// Migration subsection for [`SC144UartState`] clock.
+static VMSTATE_SC144UART_CLOCK: VMStateDescription<SC144UartState> =
+    VMStateDescriptionBuilder::<SC144UartState>::new()
+        .name(c"sc144uart/clock")
+        .version_id(1)
+        .minimum_version_id(1)
+        .needed(&SC144UartState::clock_needed) // needed: Some(sc144uart_clock_needed),
+        .fields(vmstate_fields! {
+            vmstate_of!(SC144UartState, clock),
+        })
+        .build();
+
+impl_vmstate_struct!(
+    SC144UartRegisters,
+    VMStateDescriptionBuilder::<SC144UartRegisters>::new()
+    .name(c"sc144uart/regs")
+    .version_id(2)
+    .minimum_version_id(2)
+    .fields(vmstate_fields! {
+        vmstate_of!(SC144UartRegisters, control),
+        vmstate_of!(SC144UartRegisters, dmacr),
+        vmstate_of!(SC144UartRegisters, int_enabled),
+        vmstate_of!(SC144UartRegisters, int_level),
+        vmstate_of!(SC144UartRegisters, read_fifo),
+        vmstate_of!(SC144UartRegisters, ilpr),
+        vmstate_of!(SC144UartRegisters, ifl),
+        vmstate_of!(SC144UartRegisters, read_pos),
+        vmstate_of!(SC144UartRegisters, read_count),
+        vmstate_of!(SC144UartRegisters, read_trigger),
+    })
+    .build()
+);
+
+pub const VMSTATE_SC144UART: VMStateDescription<SC144UartState> =
+    VMStateDescriptionBuilder::<SC144UartState>::new()
+        .name(c"pl011")
+        .version_id(2)
+        .minimum_version_id(2)
+        .post_load(&SC144UartState::post_load)
+        .fields(vmstate_fields! {
+            vmstate_unused!(core::mem::size_of::<u32>()),
+            vmstate_of!(SC144UartState, regs),
+        })
+        .subsections(vmstate_subsections! {
+            VMSTATE_SC144UART_CLOCK
+        })
+        .build();

rust/hw/char/dialog_uart/src/lib.rs

@@ -0,0 +1,21 @@
+// Copyright 2024, Linaro Limited
+// Author(s): Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+//! SC144xx UART QEMU Device Model
+//!
+//! This library implements a device model for the UART device
+//! found in SC144xx DECT SoCs in QEMU.
+//!
+//! # Library crate
+//!
+//! See [`SC144State`](crate::device::SC144State) for the device model type and
+//! the [`registers`] module for register types.
+
+mod device;
+mod registers;
+mod bindings;
+
+pub use device::sc144uart_create;
+
+pub const TYPE_SC144UART: &::std::ffi::CStr = c"sc144uart";

rust/hw/char/dialog_uart/src/registers.rs

@@ -0,0 +1,195 @@
+// Copyright 2024, Linaro Limited
+// Author(s): Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+//! Device registers exposed as typed structs which are backed by arbitrary
+//! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc.
+
+// For more detail see the PL011 Technical Reference Manual DDI0183:
+// https://developer.arm.com/documentation/ddi0183/latest/
+
+use bilge::prelude::*;
+use bits::bits;
+use migration::{impl_vmstate_bitsized, impl_vmstate_forward};
+
+/*;; UART registers
+
+sfr = "UART_CTRL_REG",                  "Memory", 0xFF4900, 2, base=16
+sfr = "UART_CTRL_REG.UART_REN",         "Memory", 0xFF4900, 2, base=16, bitRange=0
+sfr = "UART_CTRL_REG.UART_TEN",         "Memory", 0xFF4900, 2, base=16, bitRange=1
+sfr = "UART_CTRL_REG.BAUDRATE",         "Memory", 0xFF4900, 2, base=16, bitRange=2-4
+sfr = "UART_CTRL_REG.TI",               "Memory", 0xFF4900, 2, base=16, bitRange=5
+sfr = "UART_CTRL_REG.RI",               "Memory", 0xFF4900, 2, base=16, bitRange=6
+sfr = "UART_CTRL_REG.UART_MODE",        "Memory", 0xFF4900, 2, base=16, bitRange=7
+sfr = "UART_CTRL_REG.IRDA_EN",          "Memory", 0xFF4900, 2, base=16, bitRange=8
+sfr = "UART_CTRL_REG.INV_URX",          "Memory", 0xFF4900, 2, base=16, bitRange=9
+sfr = "UART_CTRL_REG.INV_UTX",          "Memory", 0xFF4900, 2, base=16, bitRange=10
+
+sfr = "UART_ERROR_REG",                 "Memory", 0xFF4908, 2, base=16
+sfr = "UART_ERROR_REG.PAR_STATUS",      "Memory", 0xFF4908, 2, base=16, bitRange=0
+sfr = "UART_ERROR_REG.DMA_PARITY_ERROR", "Memory", 0xFF4908, 2, base=16, bitRange=1*/
+
+/// Offset of each register from the base memory address of the device.
+#[doc(alias = "offset")]
+#[allow(non_camel_case_types)]
+#[repr(u64)]
+#[derive(Debug, Eq, PartialEq, common::TryInto)]
+pub enum RegisterOffset {
+    /// Data Register
+    ///
+    /// has a bunch of bitflags
+    #[doc(alias = "UART_CTRL_REG")]
+    CTRL = 0x000,
+    /// RX/TX Register
+    #[doc(alias = "UART_RX_TX_REG")]
+    RXTX = 0x002,
+    /// Clear TX Interrupt Register
+    #[doc(alias = "UART_CLEAR_TX_INT_REG")]
+    CLEAR_TX_INT = 0x004,
+    /// Clear RX Interrupt Register
+    #[doc(alias = "UART_CLEAR_RX_INT_REG")]
+    CLEAR_RX_INT = 0x006,
+    /// Error Register
+    #[doc(alias = "UART_ERROR_REG")]
+    ERROR = 0x008,
+}
+
+/// Data Register, `UART_RX_TX_REG`
+///
+/// The `UART_RX_TX_REG` register is the data register;
+/// write for TX and read for RX.
+/// It is an 8-bit register, where bits 7..0 are the data.
+#[bitsize(16)]
+#[derive(Clone, Copy, Default, DebugBits, FromBits)]
+#[doc(alias = "UART_RX_TX_REG")]
+pub struct Data {
+    pub data: u8,
+    _reserved: u8,
+}
+impl_vmstate_bitsized!(Data);
+
+/// Control Register, `UART_CTRL_REG`
+///
+/// The `UART_CTRL_REG` register is the control register. It contains various
+/// enable bits, and the bits to write to set the usual outbound RS232
+/// modem control signals. All bits reset to 0 except TXE and RXE.
+#[bitsize(16)]
+#[doc(alias = "UART_CTRL_REG")]
+#[derive(Clone, Copy, DebugBits, FromBits)]
+pub struct Control {
+    /// `UART_REN` Receive enable
+    pub enable_receive: bool,
+    /// `UART_TEN` Transmit enable
+    pub enable_transmit: bool,
+    /// `BAUDRATE` Baudrate
+    pub baudrate: BaudRate,
+    /// `TI` Transmit interrupt. Read only
+    pub tx_interrupt: bool,
+    /// `RI` Receive interrupt. Read only
+    pub rx_interrupt: bool,
+    /// `UART_MODE`
+    pub uart_mode: u1,
+    /// `IRDA_EN` enable RZI mode for IrDA.
+    /// QEMU does not model this.
+    pub enable_irda: bool,
+    /// `INV_URX`
+    pub invert_rx: bool,
+    /// `INV_UTX`
+    pub invert_tx: bool,
+    /// 15:11 - Reserved, do not modify, read as zero.
+    _reserved_zero_no_modify: u5,
+}
+impl_vmstate_bitsized!(Control);
+
+impl Control {
+    pub fn reset(&mut self) {
+        *self = 0.into();
+    }
+}
+
+impl Default for Control {
+    fn default() -> Self {
+        let mut ret: Self = 0.into();
+        ret.reset();
+        ret
+    }
+}
+
+#[bitsize(3)]
+#[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)]
+/// `UART_MODE` "Enable FIFOs" or Device mode, field of [Line Control
+/// register](LineControl).
+pub enum BaudRate {
+    Baud9600 = 0b000,
+    Baud19200 = 0b001,
+    Baud57600 = 0b010,
+    Baud115200 = 0b011,
+    BaudFSYS = 0b100, // See datasheet
+    Reserved1 = 0b101,
+    Reserved2 = 0b110,
+    Reserved3 = 0b111,
+}
+
+/// Error Register, `UART_ERROR_REG`
+///
+/// The `UART_ERROR_REG` register is the error register.
+/// It contains bits related to parity errors.
+/// All bits reset to 0 except TXE and RXE.
+#[bitsize(16)]
+#[doc(alias = "UART_ERROR_REG")]
+#[derive(Clone, Copy, DebugBits, FromBits)]
+pub struct ErrorReg {
+    /// `PAR_STATUS` Indicates a parity error, updated every byte
+    pub parity_status: bool,
+    /// `DMA_PARITY_ERROR` TODO
+    pub dma_parity_error: bool,
+    /// 15:2 - Reserved, do not modify, read as zero.
+    _reserved_zero_no_modify: u14,
+}
+impl_vmstate_bitsized!(ErrorReg);
+
+impl ErrorReg {
+    pub fn reset(&mut self) {
+        *self = 0.into();
+    }
+}
+
+impl Default for ErrorReg {
+    fn default() -> Self {
+        let mut ret: Self = 0.into();
+        ret.reset();
+        ret
+    }
+}
+
+#[bitsize(1)]
+#[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)]
+/// `UART_MODE` "Enable FIFOs" or Device mode, field of [Line Control
+/// register](LineControl).
+pub enum Mode {
+    Character = 0,
+    /// 1 = transmit and receive FIFO buffers are enabled (FIFO mode).
+    FIFO = 1,
+}
+
+bits! {
+    /// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC
+    #[derive(Default)]
+    pub struct Interrupt(u32) {
+        OE = 1 << 10,
+        BE = 1 << 9,
+        PE = 1 << 8,
+        FE = 1 << 7,
+        RT = 1 << 6,
+        TX = 1 << 5,
+        RX = 1 << 4,
+        DSR = 1 << 3,
+        DCD = 1 << 2,
+        CTS = 1 << 1,
+        RI = 1 << 0,
+
+        E = bits!(Self as u32: OE | BE | PE | FE),
+        MS = bits!(Self as u32: RI | DSR | DCD | CTS),
+    }
+}
+impl_vmstate_forward!(Interrupt);

rust/hw/char/dialog_uart/wrapper.h

@@ -0,0 +1,51 @@
+/*
+ * QEMU System Emulator
+ *
+ * Copyright (c) 2024 Linaro Ltd.
+ *
+ * Authors: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+/*
+ * This header file is meant to be used as input to the `bindgen` application
+ * in order to generate C FFI compatible Rust bindings.
+ */
+
+#ifndef __CLANG_STDATOMIC_H
+#define __CLANG_STDATOMIC_H
+/*
+ * Fix potential missing stdatomic.h error in case bindgen does not insert the
+ * correct libclang header paths on its own. We do not use stdatomic.h symbols
+ * in QEMU code, so it's fine to declare dummy types instead.
+ */
+typedef enum memory_order {
+  memory_order_relaxed,
+  memory_order_consume,
+  memory_order_acquire,
+  memory_order_release,
+  memory_order_acq_rel,
+  memory_order_seq_cst,
+} memory_order;
+#endif /* __CLANG_STDATOMIC_H */
+
+#include "qemu/osdep.h"
+#include "hw/char/pl011.h"

rust/hw/char/meson.build

@@ -1 +1,2 @@
+subdir('dialog_uart')
 subdir('pl011')