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ppc/pnv: Implement POWER10 PC xscom registers for direct controls

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The PC unit in the processor core contains xscom registers that provide
low level status and control of the CPU.

This implements "direct controls", sufficient for skiboot firmware,
which uses it to send NMI IPIs between CPUs.

POWER10 is sufficiently different from POWER9 (particularly with respect
to QME and special wakeup) that it is not trivial to implement POWER9
support by reusing the code.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2024-05-16 23:44:12 +10:00
parent ca4f47752a
commit c889195508
2 changed files with 87 additions and 5 deletions
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3
include/hw/ppc/pnv_core.h
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@ -109,6 +109,9 @@ OBJECT_DECLARE_TYPE(PnvQuad, PnvQuadClass, PNV_QUAD)
struct PnvQuad {
DeviceState parent_obj;
bool special_wakeup_done;
bool special_wakeup[4];
uint32_t quad_id;
MemoryRegion xscom_regs;
MemoryRegion xscom_qme_regs;