From ce117c008ff34520c168cdd4bc561ea5cb4db4b5 Mon Sep 17 00:00:00 2001
From: fridtjof <fridtjof@das-labor.org>
Date: Wed, 13 May 2026 14:54:07 +0200
Subject: [PATCH] wip! sc14445 (sort of 14443, unknown) dummy

---
 hw/cr16c/meson.build |  1 +
 hw/cr16c/sc14445.c   | 72 ++++++++++++++++++++++++++++++++++++++++++++
 hw/cr16c/sc14445.h   | 30 ++++++++++++++++++
 3 files changed, 103 insertions(+)
 create mode 100644 hw/cr16c/sc14445.c
 create mode 100644 hw/cr16c/sc14445.h

diff --git a/hw/cr16c/meson.build b/hw/cr16c/meson.build
index e956fa0326..c67d517a36 100644
--- a/hw/cr16c/meson.build
+++ b/hw/cr16c/meson.build
@@ -1,5 +1,6 @@
 cr16c_ss = ss.source_set()
 cr16c_ss.add(files('virt.c'))
+cr16c_ss.add(files('sc14445.c'))
 cr16c_ss.add(files('sc14461.c'))
 cr16c_ss.add(files('sc14480.c'))
 cr16c_ss.add(files('de410.c'))
diff --git a/hw/cr16c/sc14445.c b/hw/cr16c/sc14445.c
new file mode 100644
index 0000000000..8aaa6fc8c6
--- /dev/null
+++ b/hw/cr16c/sc14445.c
@@ -0,0 +1,72 @@
+#include "sc14445.h"
+#include "cpu-qom.h"
+#include "system/address-spaces.h"
+#include "hw/core/cpu.h"
+#include "hw/cr16c/boot.h"
+#include "hw/misc/unimp.h"
+#include "qapi/error.h"
+#include "qemu/datadir.h"
+#include "qemu/units.h"
+
+
+static void sc14445_realize(DeviceState* dev, Error** errp)
+{
+    SC14445McuState* s = SC14445_MCU(dev);
+
+    object_initialize_child(OBJECT(dev), "cpu", &s->cpu, TYPE_CR16C_CPU);
+    object_property_set_bool(OBJECT(&s->cpu), "realized", true, &error_abort);
+
+    memory_region_init_ram(&s->non_shared_ram_or_icache, OBJECT(dev), "non_shared_ram_or_icache", 24*KiB, &error_fatal);
+    memory_region_init_ram(&s->non_shared_ram_or_dcache, OBJECT(dev), "non_shared_ram_or_dcache",  8*KiB, &error_fatal);
+    memory_region_init_ram(&s->shared_int_ram,           OBJECT(dev), "shared_int_ram",           64*KiB, &error_fatal);
+    memory_region_init_rom(&s->boot_rom,                 OBJECT(dev), "boot_rom",                  2*KiB, &error_fatal);
+    memory_region_add_subregion(get_system_memory(),  0x00000, &s->non_shared_ram_or_icache);
+    memory_region_add_subregion(get_system_memory(),  0x08000, &s->non_shared_ram_or_dcache);
+    memory_region_add_subregion(get_system_memory(),  0x10000, &s->shared_int_ram);
+    memory_region_add_subregion(get_system_memory(), 0xFEF000, &s->boot_rom);
+
+    create_unimplemented_device("mmio", 0xFF0000, 0xFFFBFF - 0xFF0000);
+
+    create_unimplemented_device("icu", 0xFFFC00, 0xFFFFFF - 0xFFFC00); // interrupt controller unit
+
+    char* bios_path = qemu_find_file(QEMU_FILE_TYPE_BIOS, "sc14445-bios.img");
+    if (!cr16c_load_firmware(&s->cpu, &s->boot_rom, bios_path)) {
+        exit(1);
+    }
+}
+
+static void sc14445_reset_hold(Object *obj, ResetType type) {
+    SC14445McuClass* mcu_class = SC14445_MCU_GET_CLASS(obj);
+    SC14445McuState* mcu_state = SC14445_MCU(obj);
+    CR16CCPU* cpu = &mcu_state->cpu;
+    CPUState* cpu_state = CPU(cpu);
+
+    if (mcu_class->parent_phases.hold) {
+        mcu_class->parent_phases.hold(obj, type);
+    }
+
+    cpu_reset(cpu_state);
+    cpu_set_pc(cpu_state, 0xFEF000);
+}
+
+static void sc14445_class_init(ObjectClass* oc, const void* data)
+{
+    DeviceClass* dc = DEVICE_CLASS(oc);
+    SC14445McuClass* sc14445 = SC14445_MCU_CLASS(oc);
+    ResettableClass *rc = RESETTABLE_CLASS(oc);
+
+    resettable_class_set_parent_phases(rc, NULL, sc14445_reset_hold, NULL, &sc14445->parent_phases);
+
+    dc->realize = sc14445_realize;
+}
+
+static const TypeInfo sc14445_mcu_types[] = {
+    {
+        .name = TYPE_SC14445_MCU,
+        .parent = TYPE_SYS_BUS_DEVICE,
+        .instance_size = sizeof(SC14445McuState),
+        .class_size = sizeof(SC14445McuClass),
+        .class_init = sc14445_class_init,
+    },
+};
+DEFINE_TYPES(sc14445_mcu_types)
diff --git a/hw/cr16c/sc14445.h b/hw/cr16c/sc14445.h
new file mode 100644
index 0000000000..c7c9810801
--- /dev/null
+++ b/hw/cr16c/sc14445.h
@@ -0,0 +1,30 @@
+#ifndef HW_SC14445_H
+#define HW_SC14445_H
+
+#include "cpu.h"
+#include "hw/sysbus.h"
+
+#define TYPE_SC14445_MCU "SC14445"
+
+typedef struct SC14445McuState SC14445McuState;
+DECLARE_INSTANCE_CHECKER(SC14445McuState, SC14445_MCU, TYPE_SC14445_MCU)
+
+struct SC14445McuState {
+    SysBusDevice parent_obj;
+
+    CR16CCPU cpu;
+
+    MemoryRegion non_shared_ram_or_icache;
+    MemoryRegion non_shared_ram_or_dcache;
+    MemoryRegion shared_int_ram;
+    MemoryRegion boot_rom;
+};
+
+typedef struct SC14445McuClass {
+    SysBusDeviceClass parent_class;
+
+    ResettablePhases parent_phases;
+} SC14445McuClass;
+DECLARE_CLASS_CHECKERS(SC14445McuClass, SC14445_MCU, TYPE_SC14445_MCU)
+
+#endif /* HW_SC14445_H */