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hw/arm/aspeed: Introduce AspeedCoprocessor class and base implementation

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Add a new AspeedCoprocessor class that defines the foundational structure for
ASPEED coprocessor models. This class encapsulates a base DeviceState with
links to system memory, clock, and peripheral components such as SCU, SCUIO,
Timer Controller, and UARTs.

Introduce the corresponding implementation file
aspeed_coprocessor_common.c, which provides the aspeed_coprocessor_realize()
method, property registration, and QOM type registration. The class is marked
as abstract and intended to serve as a common base for specific coprocessor
variants (e.g. SSP/TSP subsystems).

This establishes a reusable and extensible framework for modeling ASPEED
coprocessor devices.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251013054334.955331-10-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-10-13 13:43:21 +08:00 • committed by Cédric Le Goater
parent 21b3898a69
commit d183ef19a8
3 changed files with 95 additions and 1 deletions
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49
hw/arm/aspeed_coprocessor_common.c Normal file
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@ -0,0 +1,49 @@
/*
* ASPEED Coprocessor
*
* Copyright (C) 2025 ASPEED Technology Inc.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "system/memory.h"
#include "hw/qdev-properties.h"
#include "hw/arm/aspeed_coprocessor.h"
static void aspeed_coprocessor_realize(DeviceState *dev, Error **errp)
{
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev);
if (!s->memory) {
error_setg(errp, "'memory' link is not set");
return;
}
}
static const Property aspeed_coprocessor_properties[] = {
DEFINE_PROP_LINK("memory", AspeedCoprocessorState, memory,
TYPE_MEMORY_REGION, MemoryRegion *),
};
static void aspeed_coprocessor_class_init(ObjectClass *oc, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = aspeed_coprocessor_realize;
device_class_set_props(dc, aspeed_coprocessor_properties);
}
static const TypeInfo aspeed_coprocessor_types[] = {
{
.name = TYPE_ASPEED_COPROCESSOR,
.parent = TYPE_DEVICE,
.instance_size = sizeof(AspeedCoprocessorState),
.class_size = sizeof(AspeedCoprocessorClass),
.class_init = aspeed_coprocessor_class_init,
.abstract = true,
},
};
DEFINE_TYPES(aspeed_coprocessor_types)

3
hw/arm/meson.build
View file

@ -52,7 +52,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'fby35.c'))
arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
'aspeed_ast27x0.c',
'aspeed_ast27x0-fc.c',))
'aspeed_ast27x0-fc.c',
'aspeed_coprocessor_common.c'))
arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))

44
include/hw/arm/aspeed_coprocessor.h Normal file
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@ -0,0 +1,44 @@
/*
* ASPEED Coprocessor
*
* Copyright (C) 2025 ASPEED Technology Inc.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef ASPEED_COPROCESSOR_H
#define ASPEED_COPROCESSOR_H
#include "qom/object.h"
#include "hw/arm/aspeed_soc.h"
struct AspeedCoprocessorState {
DeviceState parent;
MemoryRegion *memory;
MemoryRegion sram;
Clock *sysclk;
AspeedSCUState scu;
AspeedSCUState scuio;
AspeedTimerCtrlState timerctrl;
SerialMM uart[ASPEED_UARTS_NUM];
};
#define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor"
OBJECT_DECLARE_TYPE(AspeedCoprocessorState, AspeedCoprocessorClass,
ASPEED_COPROCESSOR)
struct AspeedCoprocessorClass {
DeviceClass parent_class;
/** valid_cpu_types: NULL terminated array of a single CPU type. */
const char * const *valid_cpu_types;
uint32_t silicon_rev;
const hwaddr *memmap;
const int *irqmap;
int uarts_base;
int uarts_num;
};
#endif /* ASPEED_COPROCESSOR_H */