fridtjof/qemu-cr16
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

target/riscv: Conceal MO_TE within gen_fload_idx() / gen_fstore_idx()

Browse source 
All callers of gen_fload_idx() / gen_fstore_idx() set the MO_TE flag.
Set it once in the callees.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20251010155045.78220-8-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Philippe Mathieu-Daudé 2025-10-10 17:50:38 +02:00 • committed by Alistair Francis
parent 23a56ce74b
commit d46fa71ea9
1 changed files with 10 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

18
target/riscv/insn_trans/trans_xthead.c.inc
View file

@ -349,6 +349,7 @@ static bool gen_fload_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
TCGv_i64 rd = cpu_fpr[a->rd];
TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
memop |= MO_TE;
tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop);
if ((memop & MO_SIZE) == MO_32) {
gen_nanbox_s(rd, rd);
@ -369,6 +370,7 @@ static bool gen_fstore_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
TCGv_i64 rd = cpu_fpr[a->rd];
TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
memop |= MO_TE;
tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop);
return true;
@ -379,7 +381,7 @@ static bool trans_th_flrd(DisasContext *ctx, arg_th_memidx *a)
REQUIRE_XTHEADFMEMIDX(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
return gen_fload_idx(ctx, a, MO_TE | MO_UQ, false);
return gen_fload_idx(ctx, a, MO_UQ, false);
}
static bool trans_th_flrw(DisasContext *ctx, arg_th_memidx *a)
@ -387,7 +389,7 @@ static bool trans_th_flrw(DisasContext *ctx, arg_th_memidx *a)
REQUIRE_XTHEADFMEMIDX(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
return gen_fload_idx(ctx, a, MO_TE | MO_UL, false);
return gen_fload_idx(ctx, a, MO_UL, false);
}
static bool trans_th_flurd(DisasContext *ctx, arg_th_memidx *a)
@ -395,7 +397,7 @@ static bool trans_th_flurd(DisasContext *ctx, arg_th_memidx *a)
REQUIRE_XTHEADFMEMIDX(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
return gen_fload_idx(ctx, a, MO_TE | MO_UQ, true);
return gen_fload_idx(ctx, a, MO_UQ, true);
}
static bool trans_th_flurw(DisasContext *ctx, arg_th_memidx *a)
@ -403,7 +405,7 @@ static bool trans_th_flurw(DisasContext *ctx, arg_th_memidx *a)
REQUIRE_XTHEADFMEMIDX(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
return gen_fload_idx(ctx, a, MO_TE | MO_UL, true);
return gen_fload_idx(ctx, a, MO_UL, true);
}
static bool trans_th_fsrd(DisasContext *ctx, arg_th_memidx *a)
@ -411,7 +413,7 @@ static bool trans_th_fsrd(DisasContext *ctx, arg_th_memidx *a)
REQUIRE_XTHEADFMEMIDX(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
return gen_fstore_idx(ctx, a, MO_TE | MO_UQ, false);
return gen_fstore_idx(ctx, a, MO_UQ, false);
}
static bool trans_th_fsrw(DisasContext *ctx, arg_th_memidx *a)
@ -419,7 +421,7 @@ static bool trans_th_fsrw(DisasContext *ctx, arg_th_memidx *a)
REQUIRE_XTHEADFMEMIDX(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
return gen_fstore_idx(ctx, a, MO_TE | MO_UL, false);
return gen_fstore_idx(ctx, a, MO_UL, false);
}
static bool trans_th_fsurd(DisasContext *ctx, arg_th_memidx *a)
@ -427,7 +429,7 @@ static bool trans_th_fsurd(DisasContext *ctx, arg_th_memidx *a)
REQUIRE_XTHEADFMEMIDX(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
return gen_fstore_idx(ctx, a, MO_TE | MO_UQ, true);
return gen_fstore_idx(ctx, a, MO_UQ, true);
}
static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a)
@ -435,7 +437,7 @@ static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a)
REQUIRE_XTHEADFMEMIDX(ctx);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
return gen_fstore_idx(ctx, a, MO_TE | MO_UL, true);
return gen_fstore_idx(ctx, a, MO_UL, true);
}
/* XTheadFmv */