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target/arm: Add GCS cpregs

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Add isar_feature_aa64_gcs.
Enable SCR_GCSEN in scr_write.
Enable HCRX_GCSEN in hcrx_write.
Default HCRX_GCSEN on if EL2 disabled.
Add the GCSCR* and GCSPR* registers.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20251008215613.300150-32-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2025-10-08 14:55:31 -07:00 • committed by Peter Maydell
parent 8a0dda3e6b
commit d8bf1761ef
8 changed files with 132 additions and 0 deletions
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95
target/arm/cpregs-gcs.c Normal file
View file

@ -0,0 +1,95 @@
/*
* QEMU ARM CP Register GCS regiters and instructions
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "qemu/timer.h"
#include "exec/icount.h"
#include "hw/irq.h"
#include "cpu.h"
#include "cpu-features.h"
#include "cpregs.h"
#include "internals.h"
static CPAccessResult access_gcs(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
if (arm_current_el(env) < 3
&& arm_feature(env, ARM_FEATURE_EL3)
&& !(env->cp15.scr_el3 & SCR_GCSEN)) {
return CP_ACCESS_TRAP_EL3;
}
return CP_ACCESS_OK;
}
static CPAccessResult access_gcs_el0(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
if (arm_current_el(env) == 0 && !(env->cp15.gcscr_el[0] & GCSCRE0_NTR)) {
return CP_ACCESS_TRAP_EL1;
}
return access_gcs(env, ri, isread);
}
static void gcspr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/*
* Bits [2:0] are RES0, so we might as well clear them now,
* rather than upon each usage a-la GetCurrentGCSPointer.
*/
raw_write(env, ri, value & ~7);
}
static const ARMCPRegInfo gcs_reginfo[] = {
{ .name = "GCSCRE0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 5, .opc2 = 2,
.access = PL1_RW, .accessfn = access_gcs, .fgt = FGT_NGCS_EL0,
.fieldoffset = offsetof(CPUARMState, cp15.gcscr_el[0]) },
{ .name = "GCSCR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 5, .opc2 = 0,
.access = PL1_RW, .accessfn = access_gcs, .fgt = FGT_NGCS_EL1,
.nv2_redirect_offset = 0x8d0 | NV2_REDIR_NV1,
.vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 2, 5, 0),
.vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 2, 5, 0),
.fieldoffset = offsetof(CPUARMState, cp15.gcscr_el[1]) },
{ .name = "GCSCR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 5, .opc2 = 0,
.access = PL2_RW, .accessfn = access_gcs,
.fieldoffset = offsetof(CPUARMState, cp15.gcscr_el[2]) },
{ .name = "GCSCR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 5, .opc2 = 0,
.access = PL3_RW,
.fieldoffset = offsetof(CPUARMState, cp15.gcscr_el[3]) },
{ .name = "GCSPR_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 2, .crm = 5, .opc2 = 1,
.access = PL0_R | PL1_W, .accessfn = access_gcs_el0,
.fgt = FGT_NGCS_EL0, .writefn = gcspr_write,
.fieldoffset = offsetof(CPUARMState, cp15.gcspr_el[0]) },
{ .name = "GCSPR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 5, .opc2 = 1,
.access = PL1_RW, .accessfn = access_gcs,
.fgt = FGT_NGCS_EL1, .writefn = gcspr_write,
.nv2_redirect_offset = 0x8c0 | NV2_REDIR_NV1,
.vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 2, 5, 1),
.vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 2, 5, 1),
.fieldoffset = offsetof(CPUARMState, cp15.gcspr_el[1]) },
{ .name = "GCSPR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 5, .opc2 = 1,
.access = PL2_RW, .accessfn = access_gcs, .writefn = gcspr_write,
.fieldoffset = offsetof(CPUARMState, cp15.gcspr_el[2]) },
{ .name = "GCSPR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 5, .opc2 = 1,
.access = PL3_RW, .writefn = gcspr_write,
.fieldoffset = offsetof(CPUARMState, cp15.gcspr_el[2]) },
};
void define_gcs_cpregs(ARMCPU *cpu)
{
if (cpu_isar_feature(aa64_gcs, cpu)) {
define_arm_cp_regs(cpu, gcs_reginfo);
}
}

2
target/arm/cpregs.h
View file

@ -779,6 +779,8 @@ typedef enum FGTBit {
DO_BIT(HFGRTR, VBAR_EL1),
DO_BIT(HFGRTR, ICC_IGRPENN_EL1),
DO_BIT(HFGRTR, ERRIDR_EL1),
DO_REV_BIT(HFGRTR, NGCS_EL0),
DO_REV_BIT(HFGRTR, NGCS_EL1),
DO_REV_BIT(HFGRTR, NSMPRI_EL1),
DO_REV_BIT(HFGRTR, NTPIDR2_EL0),
DO_REV_BIT(HFGRTR, NPIRE0_EL1),

5
target/arm/cpu-features.h
View file

@ -1149,6 +1149,11 @@ static inline bool isar_feature_aa64_nmi(const ARMISARegisters *id)
return FIELD_EX64_IDREG(id, ID_AA64PFR1, NMI) != 0;
}
static inline bool isar_feature_aa64_gcs(const ARMISARegisters *id)
{
return FIELD_EX64_IDREG(id, ID_AA64PFR1, GCS) != 0;
}
static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
{
return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >= 1;

3
target/arm/cpu.c
View file

@ -635,6 +635,9 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int target_el)
if (cpu_isar_feature(aa64_fgt, cpu)) {
env->cp15.scr_el3 |= SCR_FGTEN;
}
if (cpu_isar_feature(aa64_gcs, cpu)) {
env->cp15.scr_el3 |= SCR_GCSEN;
}
if (cpu_isar_feature(aa64_tcr2, cpu)) {
env->cp15.scr_el3 |= SCR_TCR2EN;
}

12
target/arm/cpu.h
View file

@ -580,6 +580,9 @@ typedef struct CPUArchState {
/* NV2 register */
uint64_t vncr_el2;
uint64_t gcscr_el[4]; /* GCSCRE0_EL1, GCSCR_EL[123] */
uint64_t gcspr_el[4]; /* GCSPR_EL[0123] */
} cp15;
struct {
@ -1717,6 +1720,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
#define SCR_ENAS0 (1ULL << 36)
#define SCR_ADEN (1ULL << 37)
#define SCR_HXEN (1ULL << 38)
#define SCR_GCSEN (1ULL << 39)
#define SCR_TRNDR (1ULL << 40)
#define SCR_ENTP2 (1ULL << 41)
#define SCR_TCR2EN (1ULL << 43)
@ -1725,6 +1729,14 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
#define SCR_GPF (1ULL << 48)
#define SCR_NSE (1ULL << 62)
/* GCSCR_ELx fields */
#define GCSCR_PCRSEL (1ULL << 0)
#define GCSCR_RVCHKEN (1ULL << 5)
#define GCSCR_EXLOCKEN (1ULL << 6)
#define GCSCR_PUSHMEN (1ULL << 8)
#define GCSCR_STREN (1ULL << 9)
#define GCSCRE0_NTR (1ULL << 10)
/* Return the current FPSCR value. */
uint32_t vfp_get_fpscr(CPUARMState *env);
void vfp_set_fpscr(CPUARMState *env, uint32_t val);

10
target/arm/helper.c
View file

@ -766,6 +766,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
if (cpu_isar_feature(aa64_ecv, cpu)) {
valid_mask |= SCR_ECVEN;
}
if (cpu_isar_feature(aa64_gcs, cpu)) {
valid_mask |= SCR_GCSEN;
}
if (cpu_isar_feature(aa64_tcr2, cpu)) {
valid_mask |= SCR_TCR2EN;
}
@ -3953,6 +3956,9 @@ static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri,
if (cpu_isar_feature(aa64_sctlr2, cpu)) {
valid_mask |= HCRX_SCTLR2EN;
}
if (cpu_isar_feature(aa64_gcs, cpu)) {
valid_mask |= HCRX_GCSEN;
}
/* Clear RES0 bits. */
env->cp15.hcrx_el2 = value & valid_mask;
@ -4023,6 +4029,9 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env)
if (cpu_isar_feature(aa64_sctlr2, cpu)) {
hcrx |= HCRX_SCTLR2EN;
}
if (cpu_isar_feature(aa64_gcs, cpu)) {
hcrx |= HCRX_GCSEN;
}
return hcrx;
}
if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXEN)) {
@ -7260,6 +7269,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
define_pm_cpregs(cpu);
define_gcs_cpregs(cpu);
}
/*

3
target/arm/internals.h
View file

@ -251,6 +251,7 @@ FIELD(VSTCR, SA, 30, 1)
#define HCRX_MSCEN (1ULL << 11)
#define HCRX_TCR2EN (1ULL << 14)
#define HCRX_SCTLR2EN (1ULL << 15)
#define HCRX_GCSEN (1ULL << 22)
#define HPFAR_NS (1ULL << 63)
@ -1783,6 +1784,8 @@ void define_tlb_insn_regs(ARMCPU *cpu);
void define_at_insn_regs(ARMCPU *cpu);
/* Add the cpreg definitions for PM cpregs */
void define_pm_cpregs(ARMCPU *cpu);
/* Add the cpreg definitions for GCS cpregs */
void define_gcs_cpregs(ARMCPU *cpu);
/* Effective value of MDCR_EL2 */
static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)

2
target/arm/meson.build
View file

@ -27,6 +27,7 @@ arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files(
'cpu32-stubs.c',
))
arm_user_ss.add(files(
'cpregs-gcs.c',
'cpregs-pmu.c',
'debug_helper.c',
'helper.c',
@ -47,6 +48,7 @@ arm_common_system_ss.add(files(
'arch_dump.c',
'arm-powerctl.c',
'cortex-regs.c',
'cpregs-gcs.c',
'cpregs-pmu.c',
'cpu-irq.c',
'debug_helper.c',