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target/arm: Add isar feature tests for SME2p1, SVE2p1

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250704142112.1018902-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2025-07-04 08:19:37 -06:00 • committed by Peter Maydell
parent 81123324a5
commit d8ff459b40
2 changed files with 64 additions and 0 deletions
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63
target/arm/cpu-features.h
View file

@ -604,6 +604,11 @@ static inline bool isar_feature_aa64_rpres(const ARMISARegisters *id)
return FIELD_EX64_IDREG(id, ID_AA64ISAR2, RPRES);
}
static inline bool isar_feature_aa64_lut(const ARMISARegisters *id)
{
return FIELD_EX64_IDREG(id, ID_AA64ISAR2, LUT);
}
static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
{
/* We always set the AdvSIMD and FP fields identically. */
@ -932,6 +937,11 @@ static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) != 0;
}
static inline bool isar_feature_aa64_sve2p1(const ARMISARegisters *id)
{
return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) >=2;
}
static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
{
return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) != 0;
@ -977,6 +987,21 @@ static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id)
return FIELD_EX64_IDREG(id, ID_AA64ZFR0, F64MM) != 0;
}
static inline bool isar_feature_aa64_sve_b16b16(const ARMISARegisters *id)
{
return FIELD_EX64_IDREG(id, ID_AA64ZFR0, B16B16);
}
static inline bool isar_feature_aa64_sme_b16b16(const ARMISARegisters *id)
{
return FIELD_EX64_IDREG(id, ID_AA64SMFR0, B16B16);
}
static inline bool isar_feature_aa64_sme_f16f16(const ARMISARegisters *id)
{
return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F16F16);
}
static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id)
{
return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F64F64);
@ -992,6 +1017,44 @@ static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id)
return FIELD_EX64_IDREG(id, ID_AA64SMFR0, FA64);
}
static inline bool isar_feature_aa64_sme2(const ARMISARegisters *id)
{
return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SMEVER) != 0;
}
static inline bool isar_feature_aa64_sme2p1(const ARMISARegisters *id)
{
return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SMEVER) >= 2;
}
/*
* Combinations of feature tests, for ease of use with TRANS_FEAT.
*/
static inline bool isar_feature_aa64_sme_or_sve2p1(const ARMISARegisters *id)
{
return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2p1(id);
}
static inline bool isar_feature_aa64_sme2_or_sve2p1(const ARMISARegisters *id)
{
return isar_feature_aa64_sme2(id) || isar_feature_aa64_sve2p1(id);
}
static inline bool isar_feature_aa64_sme2p1_or_sve2p1(const ARMISARegisters *id)
{
return isar_feature_aa64_sme2p1(id) || isar_feature_aa64_sve2p1(id);
}
static inline bool isar_feature_aa64_sme2_i16i64(const ARMISARegisters *id)
{
return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_i16i64(id);
}
static inline bool isar_feature_aa64_sme2_f64f64(const ARMISARegisters *id)
{
return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_f64f64(id);
}
/*
* Feature tests for "does this exist in either 32-bit or 64-bit?"
*/

1
target/arm/cpu.h
View file

@ -2211,6 +2211,7 @@ FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4)
FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4)
FIELD(ID_AA64ISAR2, RPRFM, 48, 4)
FIELD(ID_AA64ISAR2, CSSC, 52, 4)
FIELD(ID_AA64ISAR2, LUT, 56, 4)
FIELD(ID_AA64ISAR2, ATS1A, 60, 4)
FIELD(ID_AA64PFR0, EL0, 0, 4)