fridtjof/qemu-cr16
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Revert "wip! some correctness fixes to deal with host register storage vs actual target register size"

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This reverts commit e8d1cba15aa8bcd942c87da9e7de3f6ccfd706e3.
This commit is contained in:
fridtjof 2025-08-22 01:30:20 +02:00
parent d31b85c530
commit d97f52906b
1 changed files with 1 additions and 7 deletions
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8
target/cr16c/translate.c
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@ -219,9 +219,7 @@ static void gen_compute_rrp_addr(TCGv_i32 dest, uint8_t rrp, uint32_t disp) {
static bool trans_MOV_imm(DisasContext* ctx, arg_MOV_imm* a) {
int len = (a->width == 4 ? 2 : a->width) * 8;
//tcg_gen_deposit_i32(r[a->rd], r[a->rd], tcg_constant_i32(a->imm), 0, len);
//tcg_gen_deposit_z_i32();
tcg_gen_deposit_z_i32(r[a->rd], tcg_constant_i32(a->imm), 0, len);
tcg_gen_deposit_i32(r[a->rd], r[a->rd], tcg_constant_i32(a->imm), 0, len);
if (a->width == 4 && a->rd < CR16C_FIRST_32B_REG) {
tcg_gen_movi_i32(r[a->rd + 1], a->imm >> 16);
}
@ -1453,7 +1451,6 @@ static bool trans_STOR(DisasContext *ctx, arg_STOR *a) {
gen_compute_addr_disp(temp, a->ra, a->disp, a->dbase);
gen_combine_rp(a->rs, a->width);
tcg_gen_qemu_st_i32(r[a->rs], temp, 0, unsigned_op_by_width[a->width]);
tcg_gen_andi_tl(r[a->rs], r[a->rs], 0xffff); /* make it 16 bits */
return true;
}
@ -1464,7 +1461,6 @@ static bool trans_STOR_rrp(DisasContext *ctx, arg_STOR_rrp *a) {
gen_compute_rrp_addr(temp, a->rrp, a->disp);
gen_combine_rp(a->rs, a->width);
tcg_gen_qemu_st_i32(r[a->rs], temp, 0, unsigned_op_by_width[a->width]);
tcg_gen_andi_tl(r[a->rs], r[a->rs], 0xffff); /* make it 16 bits */
return true;
}
@ -1489,7 +1485,6 @@ static bool trans_STOR_abs(DisasContext *ctx, arg_STOR_abs *a) {
gen_combine_rp(a->rs, a->width);
tcg_gen_qemu_st_i32(r[a->rs], tcg_constant_i32(addr), 0, unsigned_op_by_width[a->width]);
tcg_gen_andi_tl(r[a->rs], r[a->rs], 0xffff); /* make it 16 bits */
return true;
}
@ -1499,7 +1494,6 @@ static bool trans_STOR_ind_abs(DisasContext *ctx, arg_STOR_ind_abs *a) {
tcg_gen_addi_i32(temp, r[12 + a->ri], a->addr);
gen_combine_rp(a->rs, a->width);
tcg_gen_qemu_st_i32(r[a->rs], temp, 0, unsigned_op_by_width[a->width]);
tcg_gen_andi_tl(r[a->rs], r[a->rs], 0xffff); /* make it 16 bits */
return true;
}