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hw/riscv: Replace target_ulong uses

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20251027-feature-single-binary-hw-v1-v2-2-44478d589ae9@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Anton Johansson 2025-10-27 13:35:11 +01:00 • committed by Philippe Mathieu-Daudé
parent ad9e070998
commit dfbf777540
2 changed files with 5 additions and 3 deletions
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6
hw/riscv/riscv-iommu.c
View file

@ -26,6 +26,8 @@
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/timer.h"
#include "qemu/target-info.h"
#include "qemu/bitops.h"
#include "cpu_bits.h"
#include "riscv-iommu.h"
@ -391,9 +393,9 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
const uint64_t va_mask = (1ULL << va_len) - 1;
if (pass == S_STAGE && va_len > 32) {
target_ulong mask, masked_msbs;
uint64_t mask, masked_msbs;
mask = (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1;
mask = MAKE_64BIT_MASK(0, target_long_bits() - va_len + 1);
masked_msbs = (addr >> (va_len - 1)) & mask;
if (masked_msbs != 0 && masked_msbs != mask) {

2
hw/riscv/riscv_hart.c
View file

@ -94,7 +94,7 @@ static bool csr_qtest_callback(CharFrontend *chr, gchar **words)
g_assert(rc == 0);
csr_call(words[1], cpu, csr, &val);
qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val);
qtest_sendf(chr, "OK 0 %"PRIx64"\n", val);
return true;
}