target/arm: Implement PMOV for SME2p1/SVE2p1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-91-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
3b5257c860
commit
e421e4e972
5 changed files with 207 additions and 0 deletions
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@ -3020,3 +3020,11 @@ DEF_HELPER_FLAGS_4(sve2p1_andqv_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve2p1_andqv_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve2p1_andqv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve2p1_andqv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(pmov_pv_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(pmov_pv_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(pmov_pv_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(pmov_vp_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(pmov_vp_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(pmov_vp_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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@ -30,6 +30,7 @@
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%size_23 23:2
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%dtype_23_13 23:2 13:2
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%index3_22_19 22:1 19:2
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%index3_22_17 22:1 17:2
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%index3_19_11 19:2 11:1
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%index2_20_11 20:1 11:1
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@ -594,6 +595,22 @@ INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm
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# SVE reverse vector elements
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REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn
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# SVE move predicate to/from vector
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PMOV_pv 00000101 00 101 01 0001110 rn:5 0 rd:4 \
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&rri_esz esz=0 imm=0
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PMOV_pv 00000101 00 101 1 imm:1 0001110 rn:5 0 rd:4 &rri_esz esz=1
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PMOV_pv 00000101 01 101 imm:2 0001110 rn:5 0 rd:4 &rri_esz esz=2
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PMOV_pv 00000101 1. 101 .. 0001110 rn:5 0 rd:4 \
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&rri_esz esz=3 imm=%index3_22_17
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PMOV_vp 00000101 00 101 01 1001110 0 rn:4 rd:5 \
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&rri_esz esz=0 imm=0
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PMOV_vp 00000101 00 101 1 imm:1 1001110 0 rn:4 rd:5 &rri_esz esz=1
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PMOV_vp 00000101 01 101 imm:2 1001110 0 rn:4 rd:5 &rri_esz esz=2
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PMOV_vp 00000101 1. 101 .. 1001110 0 rn:4 rd:5 \
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&rri_esz esz=3 imm=%index3_22_17
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# SVE vector table lookup
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TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm
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@ -3035,6 +3035,56 @@ void HELPER(sve_rev_d)(void *vd, void *vn, uint32_t desc)
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}
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}
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/*
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* TODO: This could use half_shuffle64 and similar bit tricks to
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* expand blocks of bits at once.
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*/
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#define DO_PMOV_PV(NAME, ESIZE) \
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void HELPER(NAME)(void *vd, void *vs, uint32_t desc) \
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{ \
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unsigned vl = simd_oprsz(desc); \
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unsigned idx = simd_data(desc); \
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unsigned elements = vl / ESIZE; \
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ARMPredicateReg *d = vd; \
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ARMVectorReg *s = vs; \
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memset(d, 0, sizeof(*d)); \
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for (unsigned e = 0; e < elements; ++e) { \
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depositn(d->p, e * ESIZE, 1, extractn(s->d, elements * idx + e, 1)); \
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} \
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}
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DO_PMOV_PV(pmov_pv_h, 2)
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DO_PMOV_PV(pmov_pv_s, 4)
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DO_PMOV_PV(pmov_pv_d, 8)
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#undef DO_PMOV_PV
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/*
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* TODO: This could use half_unshuffle64 and similar bit tricks to
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* compress blocks of bits at once.
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*/
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#define DO_PMOV_VP(NAME, ESIZE) \
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void HELPER(NAME)(void *vd, void *vs, uint32_t desc) \
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{ \
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unsigned vl = simd_oprsz(desc); \
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unsigned idx = simd_data(desc); \
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unsigned elements = vl / ESIZE; \
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ARMVectorReg *d = vd; \
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ARMPredicateReg *s = vs; \
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if (idx == 0) { \
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memset(d, 0, vl); \
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} \
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for (unsigned e = 0; e < elements; ++e) { \
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depositn(d->d, elements * idx + e, 1, extractn(s->p, e * ESIZE, 1)); \
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} \
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}
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DO_PMOV_VP(pmov_vp_h, 2)
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DO_PMOV_VP(pmov_vp_s, 4)
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DO_PMOV_VP(pmov_vp_d, 8)
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#undef DO_PMOV_VP
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typedef void tb_impl_fn(void *, void *, void *, void *, uintptr_t, bool);
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static inline void do_tbl1(void *vd, void *vn, void *vm, uint32_t desc,
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@ -2386,6 +2386,104 @@ static gen_helper_gvec_3 * const tbx_fns[4] = {
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};
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TRANS_FEAT(TBX, aa64_sve2, gen_gvec_ool_arg_zzz, tbx_fns[a->esz], a, 0)
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static bool trans_PMOV_pv(DisasContext *s, arg_PMOV_pv *a)
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{
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static gen_helper_gvec_2 * const fns[4] = {
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NULL, gen_helper_pmov_pv_h,
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gen_helper_pmov_pv_s, gen_helper_pmov_pv_d
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};
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unsigned vl, pl, vofs, pofs;
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TCGv_i64 tmp;
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if (!dc_isar_feature(aa64_sme2p1_or_sve2p1, s)) {
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return false;
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}
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if (!sve_access_check(s)) {
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return true;
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}
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vl = vec_full_reg_size(s);
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if (a->esz != MO_8) {
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tcg_gen_gvec_2_ool(pred_full_reg_offset(s, a->rd),
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vec_full_reg_offset(s, a->rn),
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vl, vl, a->imm, fns[a->esz]);
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return true;
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}
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/*
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* Copy the low PL bytes from vector Zn, zero-extending to a
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* multiple of 8 bytes, so that Pd is properly cleared.
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*/
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pl = vl / 8;
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pofs = pred_full_reg_offset(s, a->rd);
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vofs = vec_full_reg_offset(s, a->rn);
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QEMU_BUILD_BUG_ON(sizeof(ARMPredicateReg) != 32);
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for (unsigned i = 32; i >= 8; i >>= 1) {
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if (pl & i) {
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tcg_gen_gvec_mov(MO_64, pofs, vofs, i, i);
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pofs += i;
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vofs += i;
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}
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}
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switch (pl & 7) {
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case 0:
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return true;
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case 2:
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tmp = tcg_temp_new_i64();
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tcg_gen_ld16u_i64(tmp, tcg_env, vofs + (HOST_BIG_ENDIAN ? 6 : 0));
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break;
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case 4:
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tmp = tcg_temp_new_i64();
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tcg_gen_ld32u_i64(tmp, tcg_env, vofs + (HOST_BIG_ENDIAN ? 4 : 0));
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break;
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case 6:
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tmp = tcg_temp_new_i64();
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tcg_gen_ld_i64(tmp, tcg_env, vofs);
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tcg_gen_extract_i64(tmp, tmp, 0, 48);
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break;
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default:
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g_assert_not_reached();
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}
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tcg_gen_st_i64(tmp, tcg_env, pofs);
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return true;
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}
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static bool trans_PMOV_vp(DisasContext *s, arg_PMOV_pv *a)
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{
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static gen_helper_gvec_2 * const fns[4] = {
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NULL, gen_helper_pmov_vp_h,
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gen_helper_pmov_vp_s, gen_helper_pmov_vp_d
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};
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unsigned vl;
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if (!dc_isar_feature(aa64_sme2p1_or_sve2p1, s)) {
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return false;
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}
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if (!sve_access_check(s)) {
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return true;
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}
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vl = vec_full_reg_size(s);
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if (a->esz == MO_8) {
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/*
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* The low PL bytes are copied from Pn to Zd unchanged.
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* We know that the unused portion of Pn is zero, and
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* that imm == 0, so the balance of Zd must be zeroed.
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*/
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tcg_gen_gvec_mov(MO_64, vec_full_reg_offset(s, a->rd),
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pred_full_reg_offset(s, a->rn),
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size_for_gvec(vl / 8), vl);
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} else {
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tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd),
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pred_full_reg_offset(s, a->rn),
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vl, vl, a->imm, fns[a->esz]);
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}
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return true;
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}
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static bool trans_UNPK(DisasContext *s, arg_UNPK *a)
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{
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static gen_helper_gvec_2 * const fns[4][2] = {
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@ -411,4 +411,38 @@ decode_counter(unsigned png, unsigned vl, unsigned v_esz)
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return ret;
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}
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/* Extract @len bits from an array of uint64_t at offset @pos bits. */
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static inline uint64_t extractn(uint64_t *p, unsigned pos, unsigned len)
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{
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uint64_t x;
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p += pos / 64;
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pos = pos % 64;
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x = p[0];
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if (pos + len > 64) {
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x = (x >> pos) | (p[1] << (-pos & 63));
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pos = 0;
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}
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return extract64(x, pos, len);
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}
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/* Deposit @len bits into an array of uint64_t at offset @pos bits. */
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static inline void depositn(uint64_t *p, unsigned pos,
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unsigned len, uint64_t val)
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{
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p += pos / 64;
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pos = pos % 64;
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if (pos + len <= 64) {
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p[0] = deposit64(p[0], pos, len, val);
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} else {
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unsigned len0 = 64 - pos;
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unsigned len1 = len - len0;
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p[0] = deposit64(p[0], pos, len0, val);
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p[1] = deposit64(p[1], 0, len1, val >> len0);
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}
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}
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#endif /* TARGET_ARM_VEC_INTERNAL_H */
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