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target/arm: Implement FCLAMP for SME2, SVE2p1

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This is the single vector version within SVE decode space.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250704142112.1018902-69-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2025-07-04 08:20:31 -06:00 • committed by Peter Maydell
parent c1317025d8
commit e9b743947b
2 changed files with 24 additions and 0 deletions
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2
target/arm/tcg/sve.decode
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@ -1721,3 +1721,5 @@ PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \
SCLAMP 01000100 .. 0 ..... 110000 ..... ..... @rda_rn_rm
UCLAMP 01000100 .. 0 ..... 110001 ..... ..... @rda_rn_rm
FCLAMP 01100100 .. 1 ..... 001001 ..... ..... @rda_rn_rm

22
target/arm/tcg/translate-sve.c
View file

@ -7428,6 +7428,28 @@ static void gen_uclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
TRANS_FEAT(UCLAMP, aa64_sme_or_sve2p1, gen_gvec_fn_arg_zzzz, gen_uclamp, a)
static bool trans_FCLAMP(DisasContext *s, arg_FCLAMP *a)
{
static gen_helper_gvec_3_ptr * const fn[] = {
gen_helper_sme2_bfclamp,
gen_helper_sme2_fclamp_h,
gen_helper_sme2_fclamp_s,
gen_helper_sme2_fclamp_d,
};
/* This insn uses MO_8 to encode BFloat16. */
if (a->esz == MO_8
? !dc_isar_feature(aa64_sve_b16b16, s)
: !dc_isar_feature(aa64_sme2_or_sve2p1, s)) {
return false;
}
/* So far we never optimize rda with MOVPRFX */
assert(a->rd == a->ra);
return gen_gvec_fpst_zzz(s, fn[a->esz], a->rd, a->rn, a->rm, 1,
a->esz == MO_16 ? FPST_A64_F16 : FPST_A64);
}
TRANS_FEAT(SQCVTN_sh, aa64_sme2_or_sve2p1, gen_gvec_ool_zz,
gen_helper_sme2_sqcvtn_sh, a->rd, a->rn, 0)
TRANS_FEAT(UQCVTN_sh, aa64_sme2_or_sve2p1, gen_gvec_ool_zz,