target/arm: Drop ARM_FEATURE_IWMMXT handling
We have now removed all the CPU types which had the Intel XScale extensions indicated via ARM_FEATURE_IWMMXT, so this feature bit is never set. Remove all the code that can only be reached when using this flag. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250828140422.3271703-6-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
4f0fa4bfd9
commit
effe47ff48
6 changed files with 0 additions and 117 deletions
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@ -86,7 +86,6 @@ static uint32_t get_elf_hwcap(void)
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/* probe for the extra features */
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/* EDSP is in v5TE and above */
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GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP);
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GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT);
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GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE);
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GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON);
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GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS);
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@ -76,7 +76,6 @@ abi_ulong get_elf_hwcap(CPUState *cs)
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/* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */
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GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP);
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GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT);
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GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE);
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GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON);
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GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS);
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@ -76,21 +76,7 @@ struct target_vfp_sigframe {
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struct target_user_vfp_exc ufp_exc;
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} __attribute__((__aligned__(8)));
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struct target_iwmmxt_sigframe {
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abi_ulong magic;
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abi_ulong size;
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uint64_t regs[16];
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/* Note that not all the coprocessor control registers are stored here */
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uint32_t wcssf;
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uint32_t wcasf;
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uint32_t wcgr0;
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uint32_t wcgr1;
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uint32_t wcgr2;
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uint32_t wcgr3;
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} __attribute__((__aligned__(8)));
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#define TARGET_VFP_MAGIC 0x56465001
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#define TARGET_IWMMXT_MAGIC 0x12ef842a
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struct sigframe
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{
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@ -267,25 +253,6 @@ static abi_ulong *setup_sigframe_vfp(abi_ulong *regspace, CPUARMState *env)
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return (abi_ulong*)(vfpframe+1);
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}
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static abi_ulong *setup_sigframe_iwmmxt(abi_ulong *regspace, CPUARMState *env)
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{
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int i;
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struct target_iwmmxt_sigframe *iwmmxtframe;
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iwmmxtframe = (struct target_iwmmxt_sigframe *)regspace;
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__put_user(TARGET_IWMMXT_MAGIC, &iwmmxtframe->magic);
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__put_user(sizeof(*iwmmxtframe), &iwmmxtframe->size);
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for (i = 0; i < 16; i++) {
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__put_user(env->iwmmxt.regs[i], &iwmmxtframe->regs[i]);
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}
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__put_user(env->vfp.xregs[ARM_IWMMXT_wCSSF], &iwmmxtframe->wcssf);
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__put_user(env->vfp.xregs[ARM_IWMMXT_wCASF], &iwmmxtframe->wcssf);
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__put_user(env->vfp.xregs[ARM_IWMMXT_wCGR0], &iwmmxtframe->wcgr0);
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__put_user(env->vfp.xregs[ARM_IWMMXT_wCGR1], &iwmmxtframe->wcgr1);
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__put_user(env->vfp.xregs[ARM_IWMMXT_wCGR2], &iwmmxtframe->wcgr2);
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__put_user(env->vfp.xregs[ARM_IWMMXT_wCGR3], &iwmmxtframe->wcgr3);
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return (abi_ulong*)(iwmmxtframe+1);
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}
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static void setup_sigframe(struct target_ucontext *uc,
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target_sigset_t *set, CPUARMState *env)
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{
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@ -306,9 +273,6 @@ static void setup_sigframe(struct target_ucontext *uc,
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if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
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regspace = setup_sigframe_vfp(regspace, env);
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}
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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regspace = setup_sigframe_iwmmxt(regspace, env);
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}
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/* Write terminating magic word */
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__put_user(0, regspace);
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@ -435,31 +399,6 @@ static abi_ulong *restore_sigframe_vfp(CPUARMState *env, abi_ulong *regspace)
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return (abi_ulong*)(vfpframe + 1);
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}
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static abi_ulong *restore_sigframe_iwmmxt(CPUARMState *env,
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abi_ulong *regspace)
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{
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int i;
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abi_ulong magic, sz;
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struct target_iwmmxt_sigframe *iwmmxtframe;
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iwmmxtframe = (struct target_iwmmxt_sigframe *)regspace;
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__get_user(magic, &iwmmxtframe->magic);
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__get_user(sz, &iwmmxtframe->size);
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if (magic != TARGET_IWMMXT_MAGIC || sz != sizeof(*iwmmxtframe)) {
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return 0;
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}
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for (i = 0; i < 16; i++) {
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__get_user(env->iwmmxt.regs[i], &iwmmxtframe->regs[i]);
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}
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__get_user(env->vfp.xregs[ARM_IWMMXT_wCSSF], &iwmmxtframe->wcssf);
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__get_user(env->vfp.xregs[ARM_IWMMXT_wCASF], &iwmmxtframe->wcssf);
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__get_user(env->vfp.xregs[ARM_IWMMXT_wCGR0], &iwmmxtframe->wcgr0);
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__get_user(env->vfp.xregs[ARM_IWMMXT_wCGR1], &iwmmxtframe->wcgr1);
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__get_user(env->vfp.xregs[ARM_IWMMXT_wCGR2], &iwmmxtframe->wcgr2);
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__get_user(env->vfp.xregs[ARM_IWMMXT_wCGR3], &iwmmxtframe->wcgr3);
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return (abi_ulong*)(iwmmxtframe + 1);
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}
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static int do_sigframe_return(CPUARMState *env,
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target_ulong context_addr,
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struct target_ucontext *uc)
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@ -482,12 +421,6 @@ static int do_sigframe_return(CPUARMState *env,
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return 1;
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}
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}
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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regspace = restore_sigframe_iwmmxt(env, regspace);
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if (!regspace) {
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return 1;
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}
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}
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target_restore_altstack(&uc->tuc_stack, env);
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@ -247,10 +247,6 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type)
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cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON;
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
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}
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if (arm_feature(env, ARM_FEATURE_AARCH64)) {
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/* 64 bit CPUs always start in 64 bit mode */
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env->aarch64 = true;
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@ -2610,14 +2606,10 @@ static const Property arm_cpu_properties[] = {
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static const gchar *arm_gdb_arch_name(CPUState *cs)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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if (arm_gdbstub_is_aarch64(cpu)) {
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return "aarch64";
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}
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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return "iwmmxt";
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}
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return "arm";
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}
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@ -697,14 +697,6 @@ typedef struct CPUArchState {
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*/
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uint64_t exclusive_high;
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/* iwMMXt coprocessor state. */
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struct {
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uint64_t regs[16];
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uint64_t val;
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uint32_t cregs[16];
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} iwmmxt;
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struct {
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ARMPACKey apia;
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ARMPACKey apib;
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@ -1863,16 +1855,6 @@ enum arm_cpu_mode {
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/* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
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#define QEMU_VFP_FPSCR_NZCV 0xffff
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/* iwMMXt coprocessor control registers. */
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#define ARM_IWMMXT_wCID 0
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#define ARM_IWMMXT_wCon 1
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#define ARM_IWMMXT_wCSSF 2
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#define ARM_IWMMXT_wCASF 3
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#define ARM_IWMMXT_wCGR0 8
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#define ARM_IWMMXT_wCGR1 9
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#define ARM_IWMMXT_wCGR2 10
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#define ARM_IWMMXT_wCGR3 11
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/* V7M CCR bits */
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FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
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FIELD(V7M_CCR, USERSETMPEND, 1, 1)
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@ -2442,7 +2424,6 @@ QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
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*/
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enum arm_features {
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ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
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ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
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ARM_FEATURE_V6,
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ARM_FEATURE_V6K,
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ARM_FEATURE_V7,
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@ -221,26 +221,6 @@ static const VMStateDescription vmstate_vfp = {
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}
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};
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static bool iwmmxt_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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return arm_feature(env, ARM_FEATURE_IWMMXT);
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}
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static const VMStateDescription vmstate_iwmmxt = {
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.name = "cpu/iwmmxt",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = iwmmxt_needed,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
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VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
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VMSTATE_END_OF_LIST()
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}
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};
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/* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build,
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* and ARMPredicateReg is actively empty. This triggers errors
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* in the expansion of the VMSTATE macros.
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@ -1102,7 +1082,6 @@ const VMStateDescription vmstate_arm_cpu = {
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},
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.subsections = (const VMStateDescription * const []) {
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&vmstate_vfp,
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&vmstate_iwmmxt,
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&vmstate_m,
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&vmstate_thumb2ee,
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/* pmsav7_rnr must come before pmsav7 so that we have the
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