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target/mips: Extract generic gen_lx() helper

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Extract gen_lx() from gen_mips_lx(); inline the Octeon
check in decode_opc_special3_legacy().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241111222936.59869-3-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2024-11-03 05:35:19 -03:00
parent 263ce6008f
commit f0be3f9769
2 changed files with 20 additions and 36 deletions
Download patch file Download diff file Expand all files Collapse all files

55
target/mips/tcg/translate.c
View file

@ -2036,6 +2036,15 @@ static void gen_lxr(DisasContext *ctx, TCGv reg, TCGv addr,
tcg_gen_or_tl(reg, t0, t1);
}
void gen_lx(DisasContext *ctx, int rd, int base, int index, MemOp mop)
{
TCGv t0 = tcg_temp_new();
gen_base_index_addr(ctx, t0, base, index);
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | mop);
gen_store_gpr(t0, rd);
}
/* Load */
static void gen_ld(DisasContext *ctx, uint32_t opc,
int rt, int base, int offset)
@ -11328,41 +11337,6 @@ enum {
/* MIPSDSP functions. */
/* Indexed load is not for DSP only */
static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
int rd, int base, int offset)
{
TCGv t0;
if (!(ctx->insn_flags & INSN_OCTEON)) {
check_dsp(ctx);
}
t0 = tcg_temp_new();
gen_base_index_addr(ctx, t0, base, offset);
switch (opc) {
case OPC_LBUX:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
gen_store_gpr(t0, rd);
break;
case OPC_LHX:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW);
gen_store_gpr(t0, rd);
break;
case OPC_LWX:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
gen_store_gpr(t0, rd);
break;
#if defined(TARGET_MIPS64)
case OPC_LDX:
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t0, rd);
break;
#endif
}
}
static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
int ret, int v1, int v2)
{
@ -13633,15 +13607,24 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_LX_DSP:
if (!(ctx->insn_flags & INSN_OCTEON)) {
check_dsp(ctx);
}
op2 = MASK_LX(ctx->opcode);
switch (op2) {
#if defined(TARGET_MIPS64)
case OPC_LDX:
gen_lx(ctx, rd, rs, rt, MO_UQ);
break;
#endif
case OPC_LBUX:
gen_lx(ctx, rd, rs, rt, MO_UB);
break;
case OPC_LHX:
gen_lx(ctx, rd, rs, rt, MO_SW);
break;
case OPC_LWX:
gen_mips_lx(ctx, op2, rd, rs, rt);
gen_lx(ctx, rd, rs, rt, MO_SL);
break;
default: /* Invalid */
MIPS_INVAL("MASK LX");

1
target/mips/tcg/translate.h
View file

@ -169,6 +169,7 @@ void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
int get_fp_bit(int cc);
void gen_lx(DisasContext *ctx, int rd, int base, int index, MemOp mop);
void gen_ldxs(DisasContext *ctx, int base, int index, int rd);
void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp);
void gen_addiupc(DisasContext *ctx, int rx, int imm,