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qemu-sparc queue

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Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20190517' into staging

qemu-sparc queue

# gpg: Signature made Fri 17 May 2019 10:30:54 BST
# gpg:                using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg:                issuer "mark.cave-ayland@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C  C9C4 5BC2 C56F AE0F 321F

* remotes/mcayland/tags/qemu-sparc-20190517:
  MAINTAINERS: add myself for leon3
  leon3: introduce the plug and play mechanism
  leon3: add a little bootloader
  grlib, apbuart: get rid of the old-style create function
  grlib, gptimer: get rid of the old-style create function
  grlib, irqmp: get rid of the old-style create function
  leon3: fix the error message when no bios are provided
  hw/char/escc: Lower irq when transmit buffer is filled

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-05-17 15:46:37 +01:00
commit f2a930ad8c
10 changed files with 490 additions and 97 deletions
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60
include/hw/misc/grlib_ahb_apb_pnp.h Normal file
View file

@ -0,0 +1,60 @@
/*
* GRLIB AHB APB PNP
*
* Copyright (C) 2019 AdaCore
*
* Developed by :
* Frederic Konrad <frederic.konrad@adacore.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*
*/
#ifndef GRLIB_AHB_APB_PNP_H
#define GRLIB_AHB_APB_PNP_H
#define TYPE_GRLIB_AHB_PNP "grlib,ahbpnp"
#define GRLIB_AHB_PNP(obj) \
OBJECT_CHECK(AHBPnp, (obj), TYPE_GRLIB_AHB_PNP)
typedef struct AHBPnp AHBPnp;
#define TYPE_GRLIB_APB_PNP "grlib,apbpnp"
#define GRLIB_APB_PNP(obj) \
OBJECT_CHECK(APBPnp, (obj), TYPE_GRLIB_APB_PNP)
typedef struct APBPnp APBPnp;
void grlib_ahb_pnp_add_entry(AHBPnp *dev, uint32_t address, uint32_t mask,
uint8_t vendor, uint16_t device, int slave,
int type);
void grlib_apb_pnp_add_entry(APBPnp *dev, uint32_t address, uint32_t mask,
uint8_t vendor, uint16_t device, uint8_t version,
uint8_t irq, int type);
/* VENDORS */
#define GRLIB_VENDOR_GAISLER (0x01)
/* DEVICES */
#define GRLIB_LEON3_DEV (0x03)
#define GRLIB_APBMST_DEV (0x06)
#define GRLIB_APBUART_DEV (0x0C)
#define GRLIB_IRQMP_DEV (0x0D)
#define GRLIB_GPTIMER_DEV (0x11)
/* TYPE */
#define GRLIB_CPU_AREA (0x00)
#define GRLIB_APBIO_AREA (0x01)
#define GRLIB_AHBMEM_AREA (0x02)
#define GRLIB_AHB_MASTER (0x00)
#define GRLIB_AHB_SLAVE (0x01)
#endif /* GRLIB_AHB_APB_PNP_H */

78
include/hw/sparc/grlib.h
View file

@ -1,7 +1,7 @@
/*
* QEMU GRLIB Components
*
* Copyright (c) 2010-2011 AdaCore
* Copyright (c) 2010-2019 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -33,6 +33,7 @@
*/
/* IRQMP */
#define TYPE_GRLIB_IRQMP "grlib,irqmp"
typedef void (*set_pil_in_fn) (void *opaque, uint32_t pil_in);
@ -40,81 +41,10 @@ void grlib_irqmp_set_irq(void *opaque, int irq, int level);
void grlib_irqmp_ack(DeviceState *dev, int intno);
static inline
DeviceState *grlib_irqmp_create(hwaddr base,
CPUSPARCState *env,
qemu_irq **cpu_irqs,
uint32_t nr_irqs,
set_pil_in_fn set_pil_in)
{
DeviceState *dev;
assert(cpu_irqs != NULL);
dev = qdev_create(NULL, "grlib,irqmp");
qdev_prop_set_ptr(dev, "set_pil_in", set_pil_in);
qdev_prop_set_ptr(dev, "set_pil_in_opaque", env);
qdev_init_nofail(dev);
env->irq_manager = dev;
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
*cpu_irqs = qemu_allocate_irqs(grlib_irqmp_set_irq,
dev,
nr_irqs);
return dev;
}
/* GPTimer */
static inline
DeviceState *grlib_gptimer_create(hwaddr base,
uint32_t nr_timers,
uint32_t freq,
qemu_irq *cpu_irqs,
int base_irq)
{
DeviceState *dev;
int i;
dev = qdev_create(NULL, "grlib,gptimer");
qdev_prop_set_uint32(dev, "nr-timers", nr_timers);
qdev_prop_set_uint32(dev, "frequency", freq);
qdev_prop_set_uint32(dev, "irq-line", base_irq);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < nr_timers; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, cpu_irqs[base_irq + i]);
}
return dev;
}
#define TYPE_GRLIB_GPTIMER "grlib,gptimer"
/* APB UART */
static inline
DeviceState *grlib_apbuart_create(hwaddr base,
Chardev *serial,
qemu_irq irq)
{
DeviceState *dev;
dev = qdev_create(NULL, "grlib,apbuart");
qdev_prop_set_chr(dev, "chrdev", serial);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
return dev;
}
#define TYPE_GRLIB_APB_UART "grlib,apbuart"
#endif /* GRLIB_H */