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target/arm: Implement MAIR2_ELx and AMAIR2_ELx

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Enable the SCR.AIEn bit in scr_write, and test it in aien_access.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20251014195017.421681-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2025-10-23 13:12:50 +01:00 • committed by Peter Maydell
parent 97de03a0bf
commit f50cbc6e6c
4 changed files with 71 additions and 1 deletions
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2
target/arm/cpregs.h
View file

@ -806,6 +806,8 @@ typedef enum FGTBit {
DO_REV_BIT(HFGRTR, NTPIDR2_EL0),
DO_REV_BIT(HFGRTR, NPIRE0_EL1),
DO_REV_BIT(HFGRTR, NPIR_EL1),
DO_REV_BIT(HFGRTR, NMAIR2_EL1),
DO_REV_BIT(HFGRTR, NAMAIR2_EL1),
/* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */
DO_BIT(HDFGRTR, DBGBCRN_EL1),

3
target/arm/cpu.c
View file

@ -652,6 +652,9 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int target_el)
cpu_isar_feature(aa64_s2pie, cpu)) {
env->cp15.scr_el3 |= SCR_PIEN;
}
if (cpu_isar_feature(aa64_aie, cpu)) {
env->cp15.scr_el3 |= SCR_AIEN;
}
if (cpu_isar_feature(aa64_mec, cpu)) {
env->cp15.scr_el3 |= SCR_MECEN;
}

5
target/arm/cpu.h
View file

@ -447,7 +447,8 @@ typedef struct CPUArchState {
uint64_t c9_pmuserenr; /* perf monitor user enable */
uint64_t c9_pmselr; /* perf monitor counter selection register */
uint64_t c9_pminten; /* perf monitor interrupt enables */
union { /* Memory attribute redirection */
/* Memory attribute redirection */
union {
struct {
#if HOST_BIG_ENDIAN
uint64_t _unused_mair_0;
@ -467,6 +468,7 @@ typedef struct CPUArchState {
};
uint64_t mair_el[4];
};
uint64_t mair2_el[4];
union { /* vector base address register */
struct {
uint64_t _unused_vbar;
@ -1736,6 +1738,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
#define SCR_TCR2EN (1ULL << 43)
#define SCR_SCTLR2EN (1ULL << 44)
#define SCR_PIEN (1ULL << 45)
#define SCR_AIEN (1ULL << 46)
#define SCR_GPF (1ULL << 48)
#define SCR_MECEN (1ULL << 49)
#define SCR_NSE (1ULL << 62)

62
target/arm/helper.c
View file

@ -779,6 +779,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
cpu_isar_feature(aa64_s2pie, cpu)) {
valid_mask |= SCR_PIEN;
}
if (cpu_isar_feature(aa64_aie, cpu)) {
valid_mask |= SCR_AIEN;
}
if (cpu_isar_feature(aa64_mec, cpu)) {
valid_mask |= SCR_MECEN;
}
@ -6189,6 +6192,61 @@ static const ARMCPRegInfo s2pie_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.s2pir_el2) },
};
static CPAccessResult aien_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
if (arm_feature(env, ARM_FEATURE_EL3)
&& !(env->cp15.scr_el3 & SCR_AIEN)
&& arm_current_el(env) < 3) {
return CP_ACCESS_TRAP_EL3;
}
return CP_ACCESS_OK;
}
static CPAccessResult aien_el1_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
CPAccessResult ret = access_tvm_trvm(env, ri, isread);
if (ret == CP_ACCESS_OK) {
ret = aien_access(env, ri, isread);
}
return ret;
}
static const ARMCPRegInfo aie_reginfo[] = {
{ .name = "MAIR2_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1,
.access = PL1_RW, .accessfn = aien_el1_access,
.fgt = FGT_NMAIR2_EL1, .nv2_redirect_offset = 0x280 | NV2_REDIR_NV1,
.vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 10, 1, 1),
.vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 10, 2, 1),
.fieldoffset = offsetof(CPUARMState, cp15.mair2_el[1]) },
{ .name = "MAIR2_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 10, .crm = 1, .opc2 = 1,
.access = PL2_RW, .accessfn = aien_access,
.fieldoffset = offsetof(CPUARMState, cp15.mair2_el[2]) },
{ .name = "MAIR2_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 10, .crm = 1, .opc2 = 1,
.access = PL3_RW,
.fieldoffset = offsetof(CPUARMState, cp15.mair2_el[3]) },
{ .name = "AMAIR2_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 3, .opc2 = 1,
.access = PL1_RW, .accessfn = aien_el1_access,
.fgt = FGT_NAMAIR2_EL1, .nv2_redirect_offset = 0x288 | NV2_REDIR_NV1,
.vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 10, 3, 1),
.vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 10, 3, 1),
.type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "AMAIR2_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
.access = PL2_RW, .accessfn = aien_access,
.type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "AMAIR2_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 1,
.access = PL3_RW,
.type = ARM_CP_CONST, .resetvalue = 0 },
};
void register_cp_regs_for_features(ARMCPU *cpu)
{
/* Register all the coprocessor registers based on feature bits */
@ -7434,6 +7492,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
}
if (cpu_isar_feature(aa64_aie, cpu)) {
define_arm_cp_regs(cpu, aie_reginfo);
}
if (cpu_isar_feature(any_predinv, cpu)) {
define_arm_cp_regs(cpu, predinv_reginfo);
}