diff --git a/target/cr16c/insn.decode b/target/cr16c/insn.decode
index 38d87efc4e..c85730b14d 100644
--- a/target/cr16c/insn.decode
+++ b/target/cr16c/insn.decode
@@ -83,6 +83,12 @@ ANDW_imm4_16  0010 0010 .... ....                                            @pa
 ANDW_reg      0010 0011 .... ....                                            @param44
 ANDD_imm32    0000 0000 0100 ....  .... .... .... ....  .... .... .... ....  @param4_32
 ANDD_rp       0000 0000 0001 0100  1011 ---- .... ....                       @escape2_dc
+ORB_imm4_16   0010 0100 .... ....                                            @param44_imm
+ORB_reg       0010 0101 .... ....                                            @param44
+ORW_imm4_16   0010 0110 .... ....                                            @param44_imm
+ORW_reg       0010 0111 .... ....                                            @param44
+ORD_imm32     0000 0000 0101 ....  .... .... .... ....  .... .... .... ....  @param4_32
+ORD_rp        0000 0000 0001 0100  1001 ---- .... ....                       @escape2_dc
 
 ### Jumps and Linkeage
 
diff --git a/target/cr16c/translate.c b/target/cr16c/translate.c
index 1b38836323..c26dcbc823 100644
--- a/target/cr16c/translate.c
+++ b/target/cr16c/translate.c
@@ -848,6 +848,42 @@ static bool trans_ANDD_rp(DisasContext *ctx, arg_ANDD_rp *a) {
     return true;
 }
 
+static bool trans_ORB_imm4_16(DisasContext *ctx, arg_ORB_imm4_16 *a) {
+    uint16_t imm = get_imm4(ctx, a->imm) & 0xFF;
+    tcg_gen_ori_i32(r[a->rd], r[a->rd], imm);
+    return true;
+}
+
+static bool trans_ORB_reg(DisasContext *ctx, arg_ORB_reg *a) {
+    TCGv_i32 temp = tcg_temp_new_i32();
+    tcg_gen_andi_i32(temp, r[a->rs], 0xFF);
+    tcg_gen_or_i32(r[a->rd], temp, r[a->rd]);
+    return true;
+}
+
+static bool trans_ORW_imm4_16(DisasContext *ctx, arg_ORW_imm4_16 *a) {
+    uint16_t imm = get_imm4(ctx, a->imm);
+    tcg_gen_ori_i32(r[a->rd], r[a->rd], imm);
+    return true;
+}
+
+static bool trans_ORW_reg(DisasContext *ctx, arg_ORW_reg *a) {
+    tcg_gen_or_i32(r[a->rd], r[a->rd], r[a->rs]);
+    return true;
+}
+
+static bool trans_ORD_imm32(DisasContext *ctx, arg_ORD_imm32 *a) {
+    tcg_gen_ori_i32(r[a->rd], r[a->rd], a->imm);
+    tcg_gen_ori_i32(r[a->rd+1], r[a->rd+1], a->imm >> 16);
+    return true;
+}
+
+static bool trans_ORD_rp(DisasContext *ctx, arg_ORD_rp *a) {
+    tcg_gen_or_i32(r[a->rd], r[a->rd], r[a->rs]);
+    tcg_gen_or_i32(r[a->rd+1], r[a->rd+1], r[a->rs+1]);
+    return true;
+}
+
 /* Jumps and Linkage */
 
 /* For now this instruction is abused as semihosting instruction for tests */
diff --git a/tests/tcg/cr16c/test05-logic.S b/tests/tcg/cr16c/test05-logic.S
index 237e41f93e..51670da062 100644
--- a/tests/tcg/cr16c/test05-logic.S
+++ b/tests/tcg/cr16c/test05-logic.S
@@ -80,5 +80,79 @@ _start:
 	RESET
 
 
+	/*** ORB imm4/16 ***/
+	orb $0x0000, r11
+	EXPECT 0x000B, r11
+	orb $0x99FF, r10
+	EXPECT 0x01FF, r10
+	orb $0x0055, r9
+	EXPECT 0x025D, r9
+	RESET
+
+
+	/*** ORB reg ***/
+	movw $0x2200, r2
+	orb r2, r3
+	EXPECT 0x0803, r3
+	movw $0x22FF, r0
+	orb r0, r1
+	EXPECT 0x0AFF r1
+	orb r4, r7
+	EXPECT 0x0407, r7
+	RESET
+
+
+	/*** ORW imm4/16 ***/
+	orw $0x0000, r11
+	EXPECT 0x000B, r11
+	orw $0xFFFF, r10
+	EXPECT -1, r10
+	orw $0x5555, r9
+	EXPECT 0x575D, r9
+	RESET
+
+
+	/*** ORW reg ***/
+	movw $0, r2
+	orw r2, r3
+	EXPECT 0x0803, r3
+	movw $-1, r2
+	orw r2, r1
+	EXPECT -1, r1
+	orw r4, r7
+	EXPECT 0x0707, r7
+	RESET
+
+
+	/*** ORD imm4/16 ***/
+	ord $0, (r11,r10)
+	EXPECT 0x010A, r10
+	EXPECT 0x000B, r11
+	ord $0xFFFFFFFF, (r9,r8)
+	EXPECT -1, r8
+	EXPECT -1, r9
+	ord $0x55555555, (r7,r6)
+	EXPECT 0x5557, r6
+	EXPECT 0x5557, r7
+	RESET
+
+
+	/*** ORD rp ***/
+	movw $0, r0
+	movw $0, r1
+	ord (r1,r0), (r3,r2)
+	EXPECT 0x0902, r2
+	EXPECT 0x0803, r3
+	movw $-1, r0
+	movw $-1, r1
+	ord (r1,r0), (r6,r5)
+	EXPECT -1, r5
+	EXPECT -1, r6
+	ord (r10,r9), (r8,r7)
+	EXPECT 0x060F, r7
+	EXPECT 0x030A, r8
+	RESET
+
+
 	ENDING
 	FAIL_HANDLER