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hw/arm/fsl-imx8mp: Add PCIe support

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Linux checks for the PLLs in the PHY to be locked, so implement a model
emulating that.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-id: 20250223114708.1780-9-shentey@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Bernhard Beschow 2025-02-23 12:46:58 +01:00 • committed by Peter Maydell
parent a81193c3e9
commit fd1deb5301
9 changed files with 176 additions and 0 deletions
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10
include/hw/arm/fsl-imx8mp.h
View file

@ -15,6 +15,8 @@
#include "hw/misc/imx7_snvs.h"
#include "hw/misc/imx8mp_analog.h"
#include "hw/misc/imx8mp_ccm.h"
#include "hw/pci-host/designware.h"
#include "hw/pci-host/fsl_imx8m_phy.h"
#include "hw/sd/sdhci.h"
#include "qom/object.h"
#include "qemu/units.h"
@ -42,6 +44,8 @@ struct FslImx8mpState {
IMX7SNVSState snvs;
IMXSerialState uart[FSL_IMX8MP_NUM_UARTS];
SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS];
DesignwarePCIEHost pcie;
FslImx8mPciePhyState pcie_phy;
};
enum FslImx8mpMemoryRegions {
@ -197,6 +201,12 @@ enum FslImx8mpIrqs {
FSL_IMX8MP_UART4_IRQ = 29,
FSL_IMX8MP_UART5_IRQ = 30,
FSL_IMX8MP_UART6_IRQ = 16,
FSL_IMX8MP_PCI_INTA_IRQ = 126,
FSL_IMX8MP_PCI_INTB_IRQ = 125,
FSL_IMX8MP_PCI_INTC_IRQ = 124,
FSL_IMX8MP_PCI_INTD_IRQ = 123,
FSL_IMX8MP_PCI_MSI_IRQ = 140,
};
#endif /* FSL_IMX8MP_H */

28
include/hw/pci-host/fsl_imx8m_phy.h Normal file
View file

@ -0,0 +1,28 @@
/*
* i.MX8 PCIe PHY emulation
*
* Copyright (c) 2025 Bernhard Beschow <shentey@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_PCIHOST_FSLIMX8MPCIEPHY_H
#define HW_PCIHOST_FSLIMX8MPCIEPHY_H
#include "hw/sysbus.h"
#include "qom/object.h"
#include "exec/memory.h"
#define TYPE_FSL_IMX8M_PCIE_PHY "fsl-imx8m-pcie-phy"
OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mPciePhyState, FSL_IMX8M_PCIE_PHY)
#define FSL_IMX8M_PCIE_PHY_DATA_SIZE 0x800
struct FslImx8mPciePhyState {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint8_t data[FSL_IMX8M_PCIE_PHY_DATA_SIZE];
};
#endif