target-arm queue:
* support variable (runtime-determined) page sizes, for a
nearly-20% speedup of TCG for ARMv7 and v8 CPUs with 4K pages
* ptimer: add tests, support more flexible behaviour around
what happens on the "zero" tick, use ptimer for a9gtimer
* virt: ACPI: Add IORT Structure definition
* i2c: Fix SMBus read transactions to avoid double events
* timer: stm32f2xx_timer: add check for prescaler value
* QOMify musicpal, pxa2xx_gpio, strongarm, pl110
* target-arm: Implement new HLT trap for semihosting
* i2c: Add asserts for second smbus i2c_start_transfer()
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20161024' into staging
target-arm queue:
* support variable (runtime-determined) page sizes, for a
nearly-20% speedup of TCG for ARMv7 and v8 CPUs with 4K pages
* ptimer: add tests, support more flexible behaviour around
what happens on the "zero" tick, use ptimer for a9gtimer
* virt: ACPI: Add IORT Structure definition
* i2c: Fix SMBus read transactions to avoid double events
* timer: stm32f2xx_timer: add check for prescaler value
* QOMify musicpal, pxa2xx_gpio, strongarm, pl110
* target-arm: Implement new HLT trap for semihosting
* i2c: Add asserts for second smbus i2c_start_transfer()
# gpg: Signature made Mon 24 Oct 2016 18:24:17 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20161024: (32 commits)
i2c: Add asserts for second smbus i2c_start_transfer()
target-arm: Implement new HLT trap for semihosting
hw/display: QOM'ify pl110.c
hw/arm: QOM'ify strongarm.c
hw/arm: QOM'ify pxa2xx_gpio.c
hw/arm: QOM'ify musicpal.c
timer: stm32f2xx_timer: add check for prescaler value
i2c: Fix SMBus read transactions to avoid double events
timer: a9gtimer: remove loop to auto-increment comparator
ARM: Virt: ACPI: Build an IORT table with RC and ITS nodes
ACPI: Add IORT Structure definition
tests: Add tests for the ARM MPTimer
arm_mptimer: Convert to use ptimer
tests: ptimer: Replace 10000 with 1
tests: ptimer: Change the copyright comment
tests: ptimer: Add tests for "no counter round down" policy
hw/ptimer: Add "no counter round down" policy
tests: ptimer: Add tests for "no immediate reload" policy
hw/ptimer: Add "no immediate reload" policy
tests: ptimer: Add tests for "no immediate trigger" policy
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
fe4c04071f
33 changed files with 2138 additions and 304 deletions
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@ -189,6 +189,15 @@ void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val,
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/* page related stuff */
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#ifdef TARGET_PAGE_BITS_VARY
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extern bool target_page_bits_decided;
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extern int target_page_bits;
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#define TARGET_PAGE_BITS ({ assert(target_page_bits_decided); \
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target_page_bits; })
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#else
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#define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
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#endif
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#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
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#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
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#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
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@ -609,4 +609,72 @@ typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit;
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/* Masks for Flags field above */
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#define ACPI_DMAR_INCLUDE_PCI_ALL 1
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/*
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* Input Output Remapping Table (IORT)
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* Conforms to "IO Remapping Table System Software on ARM Platforms",
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* Document number: ARM DEN 0049B, October 2015
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*/
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struct AcpiIortTable {
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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uint32_t node_count;
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uint32_t node_offset;
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uint32_t reserved;
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} QEMU_PACKED;
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typedef struct AcpiIortTable AcpiIortTable;
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/*
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* IORT node types
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*/
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#define ACPI_IORT_NODE_HEADER_DEF /* Node format common fields */ \
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uint8_t type; \
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uint16_t length; \
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uint8_t revision; \
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uint32_t reserved; \
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uint32_t mapping_count; \
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uint32_t mapping_offset;
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/* Values for node Type above */
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enum {
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ACPI_IORT_NODE_ITS_GROUP = 0x00,
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ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,
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ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,
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ACPI_IORT_NODE_SMMU = 0x03,
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ACPI_IORT_NODE_SMMU_V3 = 0x04
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};
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struct AcpiIortIdMapping {
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uint32_t input_base;
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uint32_t id_count;
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uint32_t output_base;
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uint32_t output_reference;
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uint32_t flags;
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} QEMU_PACKED;
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typedef struct AcpiIortIdMapping AcpiIortIdMapping;
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struct AcpiIortMemoryAccess {
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uint32_t cache_coherency;
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uint8_t hints;
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uint16_t reserved;
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uint8_t memory_flags;
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} QEMU_PACKED;
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typedef struct AcpiIortMemoryAccess AcpiIortMemoryAccess;
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struct AcpiIortItsGroup {
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ACPI_IORT_NODE_HEADER_DEF
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uint32_t its_count;
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uint32_t identifiers[0];
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} QEMU_PACKED;
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typedef struct AcpiIortItsGroup AcpiIortItsGroup;
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struct AcpiIortRC {
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ACPI_IORT_NODE_HEADER_DEF
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AcpiIortMemoryAccess memory_properties;
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uint32_t ats_attribute;
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uint32_t pci_segment_number;
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AcpiIortIdMapping id_mapping_array[0];
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} QEMU_PACKED;
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typedef struct AcpiIortRC AcpiIortRC;
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#endif
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@ -86,6 +86,12 @@ typedef struct {
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* Returns a @HotpluggableCPUList, which describes CPUs objects which
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* could be added with -device/device_add.
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* Caller is responsible for freeing returned list.
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* @minimum_page_bits:
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* If non-zero, the board promises never to create a CPU with a page size
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* smaller than this, so QEMU can use a more efficient larger page
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* size than the target architecture's minimum. (Attempting to create
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* such a CPU will fail.) Note that changing this is a migration
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* compatibility break for the machine.
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*/
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struct MachineClass {
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/*< private >*/
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@ -124,6 +130,7 @@ struct MachineClass {
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ram_addr_t default_ram_size;
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bool option_rom_has_mr;
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bool rom_file_has_mr;
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int minimum_page_bits;
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HotplugHandler *(*get_hotplug_handler)(MachineState *machine,
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DeviceState *dev);
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@ -35,6 +35,26 @@
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*/
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#define PTIMER_POLICY_DEFAULT 0
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/* Periodic timer counter stays with "0" for a one period before wrapping
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* around. */
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#define PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD (1 << 0)
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/* Running periodic timer that has counter = limit = 0 would continuously
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* re-trigger every period. */
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#define PTIMER_POLICY_CONTINUOUS_TRIGGER (1 << 1)
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/* Starting to run with/setting counter to "0" won't trigger immediately,
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* but after a one period for both oneshot and periodic modes. */
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#define PTIMER_POLICY_NO_IMMEDIATE_TRIGGER (1 << 2)
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/* Starting to run with/setting counter to "0" won't re-load counter
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* immediately, but after a one period. */
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#define PTIMER_POLICY_NO_IMMEDIATE_RELOAD (1 << 3)
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/* Make counter value of the running timer represent the actual value and
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* not the one less. */
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#define PTIMER_POLICY_NO_COUNTER_ROUND_DOWN (1 << 4)
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/* ptimer.c */
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typedef struct ptimer_state ptimer_state;
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typedef void (*ptimer_cb)(void *opaque);
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@ -27,12 +27,9 @@
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/* State of a single timer or watchdog block */
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typedef struct {
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uint32_t count;
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uint32_t load;
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uint32_t control;
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uint32_t status;
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int64_t tick;
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QEMUTimer *timer;
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struct ptimer_state *timer;
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qemu_irq irq;
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MemoryRegion iomem;
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} TimerBlock;
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@ -81,6 +81,18 @@ bool tcg_enabled(void);
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void cpu_exec_init_all(void);
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/**
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* set_preferred_target_page_bits:
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* @bits: number of bits needed to represent an address within the page
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*
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* Set the preferred target page size (the actual target page
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* size may be smaller than any given CPU's preference).
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* Returns true on success, false on failure (which can only happen
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* if this is called after the system has already finalized its
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* choice of page size and the requested page size is smaller than that).
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*/
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bool set_preferred_target_page_bits(int bits);
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/**
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* Sends a (part of) iovec down a socket, yielding when the socket is full, or
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* Receives data into a (part of) iovec from a socket,
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Reference in a new issue