Commit graph

122988 commits

Author SHA1 Message Date
Richard Henderson
80e865668d accel/tcg: Simplify CPU_TLB_DYN_MAX_BITS
Stop taking TARGET_VIRT_ADDR_SPACE_BITS into account.

Since we currently bound CPU_TLB_DYN_MAX_BITS to 22,
the new bound with a 4k page size is 20, which isn't
so different.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30 12:45:05 -07:00
Richard Henderson
77ad412b32 accel/tcg: Convert TARGET_HAS_PRECISE_SMC to TCGCPUOps.precise_smc
Instead of having a compile-time TARGET_HAS_PRECISE_SMC definition,
have each target set the 'precise_smc' field in the TCGCPUOps
structure.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30 12:45:05 -07:00
Richard Henderson
7fa0f4a70c accel/tcg: Add CPUState arg to tb_invalidate_phys_range_fast
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30 12:45:05 -07:00
Richard Henderson
072e057ed9 accel/tcg: Add CPUState arg to tb_invalidate_phys_range
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30 12:45:05 -07:00
Richard Henderson
4af02681ff accel/tcg: Merge tb_invalidate_phys_range{__locked}
Merge tb_invalidate_phys_page_fast__locked into its
only caller, tb_invalidate_phys_range_fast.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30 12:45:05 -07:00
Richard Henderson
e4ad80ceac accel/tcg: Add CPUState arg to tb_invalidate_phys_page_range__locked
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30 12:45:05 -07:00
Richard Henderson
00f708841f accel/tcg: Add CPUState argument to tb_invalidate_phys_page_unwind
Replace existing usage of current_cpu.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30 12:45:05 -07:00
Richard Henderson
43625e35d9 accel/tcg: Add CPUState argument to page_unprotect
In the next patch, page_unprotect will need to pass
the CPUState to tb_invalidate_phys_page_unwind.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30 12:45:05 -07:00
Pierrick Bouvier
dce324fa06 docs/devel/build-environment: enhance MSYS2 instructions
Add missing prerequisite packages, and use more explicit makepkg
command.

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250430181047.2043492-1-pierrick.bouvier@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-04-30 20:44:20 +02:00
Philippe Mathieu-Daudé
3581760008 hw/rtc/mc146818rtc: Drop pre-v3 migration stream support
mc146818rtc's migration stream is at version 3 since commit
56038ef623 ("RTC: Update the RTC clock only when reading it")
from 12 years ago, released in QEMU v1.3.0!
No versioned machines are that old, we can safely remove
support for older streams and the qdev_set_legacy_instance_id()
call.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Message-ID: <20250115210048.25396-1-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-04-30 20:44:20 +02:00
Thomas Huth
c6d82df70e meson.build: Put the D-Bus summary into the UI section
We've got a dedicated section for UI options nowadays, so the
D-Bus display should get reported here, too.

Message-ID: <20250325055125.253669-1-thuth@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-04-30 20:44:20 +02:00
Thomas Huth
bcfee4938f tests/functional/test_ppc64_pseries: Skip test_ppc64_linux_smt_boot if necessary
The test_ppc64_linux_smt_boot function lacks the set_machine('pseries'),
so this test is currently failing in case the 'pseries' machine has not
been compiled into the binary. Add the check now to fix it.

Message-ID: <20250424085426.663377-1-thuth@redhat.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-04-30 20:44:20 +02:00
Thomas Huth
d64db833d6 Drop support for Python 3.8
Python 3.8 went "end of life" in October 2024 and Fedora 42 dropped
this version already, so the "python" CI job is currently failing.
Thus it's time to drop support for this Python version in QEMU, too.

While we're at it, also look for "python3.13" in the configure script.

Message-ID: <20250425120710.879518-1-thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-04-30 20:44:20 +02:00
Daniel P. Berrangé
6b1c744ec0 meson/configure: add 'valgrind' option & --{en, dis}able-valgrind flag
Currently valgrind debugging support for coroutine stacks is enabled
unconditionally when valgrind/valgrind.h is found. There is no way
to disable valgrind support if valgrind.h is present in the build env.

This is bad for distros, as an dependency far down the chain may cause
valgrind.h to become installed, inadvertently enabling QEMU's valgrind
debugging support. It also means if a distro wants valgrind support
there is no way to mandate this.

The solution is to add a 'valgrind' build feature to meson and thus
configure script.

Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20250425121713.1913424-1-berrange@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-04-30 20:44:01 +02:00
Stefan Hajnoczi
5134cf9b5d Pull request
Kevin's fix for the divide-by-zero in my recent discard commit, triggered when
 a host block device does not support discard.
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Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging

Pull request

Kevin's fix for the divide-by-zero in my recent discard commit, triggered when
a host block device does not support discard.

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* tag 'block-pull-request' of https://gitlab.com/stefanha/qemu:
  file-posix: Fix crash on discard_granularity == 0

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-04-30 13:34:44 -04:00
Stefan Hajnoczi
ffd642cb2c Convert TCG backend code generators to TCGOutOp structures,
decomposing the monolithic tcg_out_op functions.
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Merge tag 'pull-tcg-20250429' of https://gitlab.com/rth7680/qemu into staging

Convert TCG backend code generators to TCGOutOp structures,
decomposing the monolithic tcg_out_op functions.

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* tag 'pull-tcg-20250429' of https://gitlab.com/rth7680/qemu: (161 commits)
  tcg/sparc64: Implement CTPOP
  tcg/sparc64: Unexport use_vis3_instructions
  tcg: Remove tcg_out_op
  tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}
  tcg: Convert qemu_ld{2} to TCGOutOpLoad{2}
  tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128}
  tcg: Remove INDEX_op_qemu_st8_*
  tcg: Stash MemOp size in TCGOP_FLAGS
  tcg: Merge INDEX_op_st*_{i32,i64}
  tcg: Convert st to TCGOutOpStore
  tcg: Merge INDEX_op_ld*_{i32,i64}
  tcg: Convert ld to TCGOutOpLoad
  tcg: Formalize tcg_out_goto_ptr
  tcg: Formalize tcg_out_br
  tcg: Formalize tcg_out_mb
  tcg: Remove add2/sub2 opcodes
  tcg/tci: Implement add/sub carry opcodes
  tcg/sparc64: Implement add/sub carry opcodes
  tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc
  tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-04-30 13:34:35 -04:00
Kevin Wolf
71a30d54e6 file-posix: Fix crash on discard_granularity == 0
Block devices that don't support discard have a discard_granularity of
0. Currently, this results in a division by zero when we try to make
sure that it's a multiple of request_alignment. Only try to update
bs->bl.pdiscard_alignment when we got a non-zero discard_granularity
from sysfs.

Fixes: f605796aae ('file-posix: probe discard alignment on Linux block devices')
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-ID: <20250429155654.102735-1-kwolf@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-04-30 11:40:05 -04:00
Gautam Gala
55a494e53e target/s390x: Return UVC cmd code, RC and RRC value when DIAG 308 Subcode 10 fails to enter secure mode
Extend DIAG308 subcode 10 to return the UVC RC, RRC and command code
in bit positions 32-47, 16-31, and 0-15 of register R1 + 1 if the
function does not complete successfully (in addition to the
previously returned diag response code in bit position 47-63).

Reviewed-by: Janosch Frank <frankja@linux.ibm.com>
Signed-off-by: Gautam Gala <ggala@linux.ibm.com>
Reviewed-by: Steffen Eiden <seiden@linux.ibm.com>
Message-ID: <20250423080915.1048123-4-ggala@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-04-30 09:48:57 +02:00
Gautam Gala
e27cbd17dd target/s390x: Introduce function when exiting PV
Replace an existing macro (s390_pv_cmd_exit) that looks like
a function with an actual function. The function will be used
when exiting PV instead of the macro.

Reviewed-by: Steffen Eiden <seiden@linux.ibm.com>
Reviewed-by: Janosch Frank <frankja@linux.ibm.com>
Signed-off-by: Gautam Gala <ggala@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20250423080915.1048123-3-ggala@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-04-30 09:48:57 +02:00
Gautam Gala
2e6a9f03ba target/s390x: Introduce constant when checking if PV header couldn't be decrypted
Introduce a named constant when checking the Set Secure Configuration parameters
UV call return code for the case where no valid host key was found and therefore
the PV header couldn't be decrypted (0x108).

Reviewed-by: Steffen Eiden <seiden@linux.ibm.com>
Reviewed-by: Janosch Frank <frankja@linux.ibm.com>
Signed-off-by: Gautam Gala <ggala@linux.ibm.com>
Message-ID: <20250423080915.1048123-2-ggala@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-04-30 09:48:57 +02:00
Vincent Vanlaer
23743ab282 block: move commit_run loop to separate function
Signed-off-by: Vincent Vanlaer <libvirt-e6954efa@volkihar.be>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Message-Id: <20241026163010.2865002-3-libvirt-e6954efa@volkihar.be>
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
2025-04-29 12:55:28 +03:00
Vincent Vanlaer
71365ee433 block: get type of block allocation in commit_run
bdrv_co_common_block_status_above not only returns whether the block is
allocated, but also if it contains zeroes.

Signed-off-by: Vincent Vanlaer <libvirt-e6954efa@volkihar.be>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Message-Id: <20241026163010.2865002-2-libvirt-e6954efa@volkihar.be>
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
2025-04-29 12:55:28 +03:00
Richard Henderson
70ab4f4ed9 tcg/sparc64: Implement CTPOP
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
33b6c61cce tcg/sparc64: Unexport use_vis3_instructions
This variable is no longer used outside tcg-target.c.inc.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
eafecf0805 tcg: Remove tcg_out_op
All integer opcodes are now converted to TCGOutOp.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
86fe5c2597 tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
3bedb9d3e2 tcg: Convert qemu_ld{2} to TCGOutOpLoad{2}
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
aae2456ac0 tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128}
Merge into INDEX_op_{ld,st,ld2,st2}, where "2" indicates that two
inputs or outputs are required. This simplifies the processing of
i64/i128 depending on host word size.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
33aba058c8 tcg: Remove INDEX_op_qemu_st8_*
The i386 backend can now check TCGOP_FLAGS to select
the correct set of constraints.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
bf7ca5fb30 tcg: Stash MemOp size in TCGOP_FLAGS
This will enable removing INDEX_op_qemu_st8_*_i32,
by exposing the operand size to constraint selection.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
a28f151d61 tcg: Merge INDEX_op_st*_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
4a686aa9d9 tcg: Convert st to TCGOutOpStore
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
e996804d40 tcg: Merge INDEX_op_ld*_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
0de5c9d1f5 tcg: Convert ld to TCGOutOpLoad
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
fee03fdde3 tcg: Formalize tcg_out_goto_ptr
Split these functions out from tcg_out_op.
Define outop_goto_ptr generically.
Call tcg_out_goto_ptr from tcg_reg_alloc_op.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
3752a5a5ba tcg: Formalize tcg_out_br
Split these functions out from tcg_out_op.
Call it directly from tcg_gen_code.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
e038696c92 tcg: Formalize tcg_out_mb
Most tcg backends already have a function for this;
the rest can split one out from tcg_out_op.
Call it directly from tcg_gen_code.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
f2b1708e80 tcg: Remove add2/sub2 opcodes
All uses have been replaced by add/sub carry opcodes.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
4b0ee858be tcg/tci: Implement add/sub carry opcodes
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
9dd1ea33b2 tcg/sparc64: Implement add/sub carry opcodes
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
809069eaa3 tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc
Pass the sparc COND_* value not the tcg TCG_COND_* value.
This makes the usage within add2/sub2 clearer.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
41dd55c79c tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
cda7f93fa2 tcg/s390x: Implement add/sub carry opcodes
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
19b9fc2a39 tcg/s390x: Add TCG_CT_CONST_N32
We were using S32 | U32 for add2/sub2.  But the ALGFI and SLGFI
insns that implement this both have uint32_t immediates.
This makes the composite range balanced and
enables use of -0xffffffff ... -0x80000001.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
1b6e25e300 tcg/s390x: Honor carry_live in tcg_out_movi
Do not clobber flags if they're live.  Required in order
to perform register allocation on add/sub carry opcodes.
LA and AGHI are the same size, so use LA unconditionally.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
2329da9605 tcg/ppc: Implement add/sub carry opcodes
Tested-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
b15c0d11a2 tcg/arm: Implement add/sub carry opcodes
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
75351891b8 tcg/aarch64: Implement add/sub carry opcodes
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
867878c112 target/tricore: Use tcg_gen_addcio_i32 for gen_addc_CC
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
Richard Henderson
6ed4d97ff7 target/sparc: Use tcg_gen_addcio_tl for gen_op_addcc_int
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00