3 commits

Author	SHA1	Message	Date
Yongbok Kim	9253773cb7	target/mips: Add support for emulation of CRC32 instructions ... Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions. Reuse zlib crc32() and Linux crc32c(). Corresponding disassembly has been added in commit 99029be1c2 ("target/mips: Add implementation of GINVT instruction"). Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com> Reviewed-by: Aleksandar Rikalo <arikalo@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <PA4PR09MB486489692D843DDFC25F3CF1846B2@PA4PR09MB4864.eurprd09.prod.outlook.com>	2025-07-15 00:07:46 +02:00
Philippe Mathieu-Daudé	34fe9fa368	target/mips: Rename 'rtype' as 'r' ... We'll soon have more opcode and decoded arguments, and 'rtype' is not very helpful. Naming it simply 'r' ease reviewing the .decode files when we have many opcodes. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-5-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>	2021-08-25 13:02:14 +02:00
Philippe Mathieu-Daudé	12f79f1173	target/mips: Merge 32-bit/64-bit Release6 decodetree definitions ... We don't need to maintain 2 sets of decodetree definitions. Merge them into a single file. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-4-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>	2021-08-25 13:02:06 +02:00

Renamed from target/mips/tcg/mips32r6.decode (Browse further)