20a785d631
This commit moves the Nvidia GB200NVL BMC machine implementation out of aspeed.c into a new standalone file aspeed_ast2600_gb200nvl.c. This refactor continues the modularization effort for Aspeed platform support, placing each board’s initialization logic in its own dedicated source file. It improves code maintainability, readability, and simplifies adding new platforms without increasing the complexity of aspeed.c. Key updates include: - Moved GB200NVL_BMC_HW_STRAP1 and GB200NVL_BMC_HW_STRAP2 macro definitions into the new file. - Moved gb200nvl_bmc_i2c_init() and its related FRUID setup into the new file. - Moved aspeed_machine_gb200nvl_class_init() and type registration logic out of aspeed.c. - Removed gb200nvl_bmc_fruid[] and its length definition from aspeed_eeprom.c/h. - Added aspeed_ast2600_gb200nvl.c to the Meson build system (meson.build). - Cleaned up all GB200NVL-specific code and data from aspeed.c and aspeed_eeprom.c. No functional changes. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20251104031325.146374-25-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
111 lines
4 KiB
C
111 lines
4 KiB
C
/*
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* Nvidia GB200NVL
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*
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* Copyright 2016 IBM Corp.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/arm/machines-qom.h"
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#include "hw/arm/aspeed.h"
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#include "hw/arm/aspeed_soc.h"
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#include "hw/nvram/eeprom_at24c.h"
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/* GB200NVL hardware value */
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#define GB200NVL_BMC_HW_STRAP1 0x000000C0
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#define GB200NVL_BMC_HW_STRAP2 0x00000003
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#define GB200NVL_BMC_RAM_SIZE ASPEED_RAM_SIZE(1 * GiB)
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static const uint8_t gb200nvl_bmc_fruid[] = {
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0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, 0x19, 0x1f,
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0x0f, 0xe6, 0xc6, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0xc5, 0x50, 0x33,
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0x38, 0x30, 0x39, 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38,
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0x30, 0x30, 0x31, 0x35, 0x30, 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33,
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0x38, 0x30, 0x39, 0x2d, 0x30, 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30,
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0xc0, 0x01, 0x01, 0xd6, 0x4d, 0x41, 0x43, 0x3a, 0x20, 0x33, 0x43, 0x3a,
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0x36, 0x44, 0x3a, 0x36, 0x36, 0x3a, 0x31, 0x34, 0x3a, 0x43, 0x38, 0x3a,
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0x37, 0x41, 0xc1, 0x3b, 0x01, 0x09, 0x19, 0xc6, 0x4e, 0x56, 0x49, 0x44,
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0x49, 0x41, 0xc9, 0x50, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x42, 0x4d, 0x43,
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0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x30,
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0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, 0xc4, 0x41, 0x45, 0x2e, 0x31,
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0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, 0x30, 0x30, 0x31,
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0x35, 0x30, 0xc0, 0xc4, 0x76, 0x30, 0x2e, 0x31, 0xc1, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0xb4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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};
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static const size_t gb200nvl_bmc_fruid_len = sizeof(gb200nvl_bmc_fruid);
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static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc)
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{
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AspeedSoCState *soc = bmc->soc;
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I2CBus *i2c[15] = {};
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DeviceState *dev;
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for (int i = 0; i < sizeof(i2c) / sizeof(i2c[0]); i++) {
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if ((i == 11) || (i == 12) || (i == 13)) {
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continue;
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}
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i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
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}
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/* Bus 5 Expander */
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aspeed_create_pca9554(soc, 4, 0x21);
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/* Mux I2c Expanders */
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i2c_slave_create_simple(i2c[5], "pca9546", 0x71);
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i2c_slave_create_simple(i2c[5], "pca9546", 0x72);
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i2c_slave_create_simple(i2c[5], "pca9546", 0x73);
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i2c_slave_create_simple(i2c[5], "pca9546", 0x75);
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i2c_slave_create_simple(i2c[5], "pca9546", 0x76);
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i2c_slave_create_simple(i2c[5], "pca9546", 0x77);
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/* Bus 10 */
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dev = DEVICE(aspeed_create_pca9554(soc, 9, 0x20));
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/* Set FPGA_READY */
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object_property_set_str(OBJECT(dev), "pin1", "high", &error_fatal);
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aspeed_create_pca9554(soc, 9, 0x21);
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at24c_eeprom_init(i2c[9], 0x50, 64 * KiB);
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at24c_eeprom_init(i2c[9], 0x51, 64 * KiB);
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/* Bus 11 */
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at24c_eeprom_init_rom(i2c[10], 0x50, 256, gb200nvl_bmc_fruid,
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gb200nvl_bmc_fruid_len);
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}
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static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc,
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const void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
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mc->desc = "Nvidia GB200NVL BMC (Cortex-A7)";
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amc->soc_name = "ast2600-a3";
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amc->hw_strap1 = GB200NVL_BMC_HW_STRAP1;
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amc->hw_strap2 = GB200NVL_BMC_HW_STRAP2;
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amc->fmc_model = "mx66u51235f";
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amc->spi_model = "mx66u51235f";
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amc->num_cs = 2;
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amc->spi2_model = "mx66u51235f";
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amc->num_cs2 = 1;
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amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
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amc->i2c_init = gb200nvl_bmc_i2c_init;
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mc->default_ram_size = GB200NVL_BMC_RAM_SIZE;
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aspeed_machine_class_init_cpus_defaults(mc);
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aspeed_machine_ast2600_class_emmc_init(oc);
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}
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static const TypeInfo aspeed_ast2600_gb200nvl_types[] = {
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{
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.name = MACHINE_TYPE_NAME("gb200nvl-bmc"),
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.parent = TYPE_ASPEED_MACHINE,
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.class_init = aspeed_machine_gb200nvl_class_init,
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.interfaces = arm_machine_interfaces,
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}
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};
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DEFINE_TYPES(aspeed_ast2600_gb200nvl_types)
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