10e377246d
In the original model, each subsystem (PSP, SSP, and TSP) created its own
set of 13 UART devices, resulting in a total of 39 UART instances. However,
on real AST2700 hardware, there is only one set of 13 UARTs shared among
all processors.
This commit reworks the UART handling to correctly model the shared
hardware design. The PSP now creates the full set of 13 UART instances,
while the SSP and TSP link to the corresponding shared UART device
through object properties.
Changes include:
- Add "DEFINE_PROP_LINK("uart", ...)" and "DEFINE_PROP_INT32("uart-dev", ...)"
to allow each coprocessor to reference a specific shared UART instance.
- Modify SSP to link to PSP’s UART4, and TSP to link to PSP’s UART7.
- Introduce "uart_alias" to remap the UART’s MMIO region into the coprocessor’s
memory space.
- Redirect the UART interrupt to the coprocessor’s NVIC, replacing the
default routing to the PSP’s GIC.
With this change, only one set of 13 UART devices is instantiated by the PSP,
while the SSP and TSP reuse them via aliasing and shared interrupt routing,
matching the real AST2700 hardware behavior.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-7-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
297 lines
11 KiB
C
297 lines
11 KiB
C
/*
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* ASPEED Ast27x0 SSP Coprocessor
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*
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* Copyright (C) 2025 ASPEED Technology Inc.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/qdev-clock.h"
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#include "hw/misc/unimp.h"
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#include "hw/arm/aspeed_soc.h"
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#include "hw/arm/aspeed_coprocessor.h"
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#define AST2700_SSP_SDRAM_SIZE (512 * MiB)
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static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
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[ASPEED_DEV_SDRAM] = 0x00000000,
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[ASPEED_DEV_SRAM] = 0x70000000,
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[ASPEED_DEV_INTC] = 0x72100000,
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[ASPEED_DEV_SCU] = 0x72C02000,
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[ASPEED_DEV_SCUIO] = 0x74C02000,
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[ASPEED_DEV_UART0] = 0x74C33000,
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[ASPEED_DEV_UART1] = 0x74C33100,
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[ASPEED_DEV_UART2] = 0x74C33200,
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[ASPEED_DEV_UART3] = 0x74C33300,
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[ASPEED_DEV_UART4] = 0x72C1A000,
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[ASPEED_DEV_INTCIO] = 0x74C18000,
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[ASPEED_DEV_IPC0] = 0x72C1C000,
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[ASPEED_DEV_IPC1] = 0x74C39000,
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[ASPEED_DEV_UART5] = 0x74C33400,
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[ASPEED_DEV_UART6] = 0x74C33500,
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[ASPEED_DEV_UART7] = 0x74C33600,
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[ASPEED_DEV_UART8] = 0x74C33700,
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[ASPEED_DEV_UART9] = 0x74C33800,
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[ASPEED_DEV_UART10] = 0x74C33900,
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[ASPEED_DEV_UART11] = 0x74C33A00,
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[ASPEED_DEV_UART12] = 0x74C33B00,
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[ASPEED_DEV_TIMER1] = 0x72C10000,
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};
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static const int aspeed_soc_ast27x0ssp_irqmap[] = {
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[ASPEED_DEV_SCU] = 12,
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[ASPEED_DEV_UART0] = 164,
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[ASPEED_DEV_UART1] = 164,
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[ASPEED_DEV_UART2] = 164,
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[ASPEED_DEV_UART3] = 164,
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[ASPEED_DEV_UART4] = 8,
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[ASPEED_DEV_UART5] = 164,
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[ASPEED_DEV_UART6] = 164,
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[ASPEED_DEV_UART7] = 164,
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[ASPEED_DEV_UART8] = 164,
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[ASPEED_DEV_UART9] = 164,
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[ASPEED_DEV_UART10] = 164,
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[ASPEED_DEV_UART11] = 164,
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[ASPEED_DEV_UART12] = 164,
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[ASPEED_DEV_TIMER1] = 16,
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};
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/* SSPINT 164 */
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static const int ast2700_ssp132_ssp164_intcmap[] = {
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[ASPEED_DEV_UART0] = 7,
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[ASPEED_DEV_UART1] = 8,
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[ASPEED_DEV_UART2] = 9,
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[ASPEED_DEV_UART3] = 10,
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[ASPEED_DEV_UART5] = 11,
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[ASPEED_DEV_UART6] = 12,
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[ASPEED_DEV_UART7] = 13,
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[ASPEED_DEV_UART8] = 14,
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[ASPEED_DEV_UART9] = 15,
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[ASPEED_DEV_UART10] = 16,
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[ASPEED_DEV_UART11] = 17,
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[ASPEED_DEV_UART12] = 18,
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};
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struct nvic_intc_irq_info {
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int irq;
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int intc_idx;
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int orgate_idx;
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const int *ptr;
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};
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static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = {
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{160, 1, 0, NULL},
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{161, 1, 1, NULL},
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{162, 1, 2, NULL},
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{163, 1, 3, NULL},
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{164, 1, 4, ast2700_ssp132_ssp164_intcmap},
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{165, 1, 5, NULL},
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{166, 1, 6, NULL},
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{167, 1, 7, NULL},
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{168, 1, 8, NULL},
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{169, 1, 9, NULL},
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{128, 0, 1, NULL},
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{129, 0, 2, NULL},
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{130, 0, 3, NULL},
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{131, 0, 4, NULL},
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{132, 0, 5, ast2700_ssp132_ssp164_intcmap},
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{133, 0, 6, NULL},
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{134, 0, 7, NULL},
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{135, 0, 8, NULL},
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{136, 0, 9, NULL},
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};
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static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedCoprocessorState *s,
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int dev)
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{
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Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_COPROCESSOR(s);
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AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
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int or_idx;
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int idx;
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int i;
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for (i = 0; i < ARRAY_SIZE(ast2700_ssp_intcmap); i++) {
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if (sc->irqmap[dev] == ast2700_ssp_intcmap[i].irq) {
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assert(ast2700_ssp_intcmap[i].ptr);
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or_idx = ast2700_ssp_intcmap[i].orgate_idx;
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idx = ast2700_ssp_intcmap[i].intc_idx;
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return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
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ast2700_ssp_intcmap[i].ptr[dev]);
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}
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}
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return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
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}
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static void aspeed_soc_ast27x0ssp_init(Object *obj)
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{
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Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_COPROCESSOR(obj);
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AspeedCoprocessorState *s = ASPEED_COPROCESSOR(obj);
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object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
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s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
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object_initialize_child(obj, "intc0", &a->intc[0],
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TYPE_ASPEED_2700SSP_INTC);
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object_initialize_child(obj, "intc1", &a->intc[1],
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TYPE_ASPEED_2700SSP_INTCIO);
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object_initialize_child(obj, "timerctrl", &s->timerctrl,
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TYPE_UNIMPLEMENTED_DEVICE);
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object_initialize_child(obj, "ipc0", &a->ipc[0],
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TYPE_UNIMPLEMENTED_DEVICE);
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object_initialize_child(obj, "ipc1", &a->ipc[1],
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TYPE_UNIMPLEMENTED_DEVICE);
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object_initialize_child(obj, "scuio", &a->scuio,
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TYPE_UNIMPLEMENTED_DEVICE);
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}
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static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
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{
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Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_COPROCESSOR(dev_soc);
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AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev_soc);
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AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
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DeviceState *armv7m;
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g_autofree char *sdram_name = NULL;
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int i;
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if (!clock_has_source(s->sysclk)) {
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error_setg(errp, "sysclk clock must be wired up by the board code");
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return;
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}
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/* AST27X0 SSP Core */
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armv7m = DEVICE(&a->armv7m);
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qdev_prop_set_uint32(armv7m, "num-irq", 256);
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qdev_prop_set_string(armv7m, "cpu-type",
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aspeed_soc_cpu_type(sc->valid_cpu_types));
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qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
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object_property_set_link(OBJECT(&a->armv7m), "memory",
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OBJECT(s->memory), &error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
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/* SDRAM */
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sdram_name = g_strdup_printf("aspeed.sdram.%d",
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CPU(a->armv7m.cpu)->cpu_index);
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if (!memory_region_init_ram(&s->sdram, OBJECT(s), sdram_name,
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AST2700_SSP_SDRAM_SIZE, errp)) {
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return;
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}
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memory_region_add_subregion(s->memory,
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sc->memmap[ASPEED_DEV_SDRAM],
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&s->sdram);
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/* SRAM */
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memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias",
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s->sram, 0, memory_region_size(s->sram));
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memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
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&s->sram_alias);
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/* SCU */
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memory_region_init_alias(&s->scu_alias, OBJECT(s), "scu.alias",
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&s->scu->iomem, 0,
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memory_region_size(&s->scu->iomem));
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memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
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&s->scu_alias);
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/* INTC */
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if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
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return;
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}
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aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[0]), 0,
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sc->memmap[ASPEED_DEV_INTC]);
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/* INTCIO */
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if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
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return;
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}
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aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
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sc->memmap[ASPEED_DEV_INTCIO]);
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/* irq source orgates -> INTC0 */
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for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++) {
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qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
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qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
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}
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for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_outpins; i++) {
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assert(i < ARRAY_SIZE(ast2700_ssp_intcmap));
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sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
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qdev_get_gpio_in(DEVICE(&a->armv7m),
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ast2700_ssp_intcmap[i].irq));
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}
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/* irq source orgates -> INTCIO */
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for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_inpins; i++) {
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qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
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qdev_get_gpio_in(DEVICE(&a->intc[1]), i));
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}
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/* INTCIO -> INTC */
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for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_outpins; i++) {
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sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
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qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
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}
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/* UART */
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memory_region_init_alias(&s->uart_alias, OBJECT(s), "uart.alias",
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&s->uart->serial.io, 0,
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memory_region_size(&s->uart->serial.io));
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memory_region_add_subregion(s->memory, sc->memmap[s->uart_dev],
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&s->uart_alias);
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/*
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* Redirect the UART interrupt to the NVIC, replacing the default routing
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* to the PSP's GIC.
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*/
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sysbus_connect_irq(SYS_BUS_DEVICE(s->uart), 0,
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aspeed_soc_ast27x0ssp_get_irq(s, s->uart_dev));
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aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),
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"aspeed.timerctrl",
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sc->memmap[ASPEED_DEV_TIMER1], 0x200);
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aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[0]),
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"aspeed.ipc0",
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sc->memmap[ASPEED_DEV_IPC0], 0x1000);
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aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[1]),
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"aspeed.ipc1",
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sc->memmap[ASPEED_DEV_IPC1], 0x1000);
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aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio),
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"aspeed.scuio",
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sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
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}
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static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
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const void *data)
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{
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static const char * const valid_cpu_types[] = {
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ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */
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NULL
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};
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DeviceClass *dc = DEVICE_CLASS(klass);
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AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_CLASS(dc);
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/* Reason: The Aspeed Coprocessor can only be instantiated from a board */
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dc->user_creatable = false;
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dc->realize = aspeed_soc_ast27x0ssp_realize;
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sc->valid_cpu_types = valid_cpu_types;
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sc->irqmap = aspeed_soc_ast27x0ssp_irqmap;
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sc->memmap = aspeed_soc_ast27x0ssp_memmap;
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}
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static const TypeInfo aspeed_soc_ast27x0ssp_types[] = {
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{
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.name = TYPE_ASPEED27X0SSP_COPROCESSOR,
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.parent = TYPE_ASPEED_COPROCESSOR,
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.instance_size = sizeof(Aspeed27x0CoprocessorState),
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.instance_init = aspeed_soc_ast27x0ssp_init,
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.class_init = aspeed_soc_ast27x0ssp_class_init,
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},
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};
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DEFINE_TYPES(aspeed_soc_ast27x0ssp_types)
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