303e8dc29f
This patch introduces an initial ASPEED PCIe PHY/host controller model to support the AST2600 SoC. It provides a simple register block with MMIO read/write callbacks, integration into the build system, and trace events for debugging. Key changes: 1. PCIe PHY MMIO read/write callbacks Implemented aspeed_pcie_phy_read() and aspeed_pcie_phy_write() to handle 32-bit register accesses. 2. Build system and Kconfig integration Added CONFIG_PCI_EXPRESS_ASPEED in hw/pci-host/Kconfig and meson rules. Updated ASPEED_SOC in hw/arm/Kconfig to imply PCI_DEVICES and select PCI_EXPRESS_ASPEED. 3. Trace events for debug New tracepoints aspeed_pcie_phy_read and aspeed_pcie_phy_write allow monitoring MMIO accesses. 4. Register space and defaults (AST2600 reference) Expose a 0x100 register space, as documented in the AST2600 datasheet. On reset, set default values: PEHR_ID: Vendor ID = ASPEED, Device ID = 0x1150 PEHR_CLASS_CODE = 0x06040006 PEHR_DATALINK = 0xD7040022 PEHR_LINK: bit[5] set to 1 to indicate link up. This provides a skeleton device for the AST2600 platform. It enables firmware to detect the PCIe link as up by default and allows future extension. This commit is the starting point of the series to introduce ASPEED PCIe Root Complex (RC) support. Based on previous work from Cédric Le Goater, the following commits in this series extend and refine the implementation: - Add a PCIe Root Port so that devices can be attached without requiring an extra bridge. - Restrict the Root Port device instantiation to the AST2600 platform. - Integrate aspeed_cfg_translate_write() to support both AST2600 and AST2700. - Add MSI support and a preliminary RC IOMMU address space. - Fix issues with MSI interrupt clearing. - Extend support to the AST2700 SoC. - Drop the AST2600 RC_L support. - Introduce PCIe RC functional tests covering both AST2600 and AST2700. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
114 lines
1.4 KiB
Text
114 lines
1.4 KiB
Text
config PAM
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bool
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config XEN_IGD_PASSTHROUGH
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bool
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default y
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depends on XEN && PCI_I440FX
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config PPC4XX_PCI
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bool
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select PCI
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config PPC440_PCIX
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bool
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select PCI
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config RAVEN_PCI
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bool
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select PCI
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select OR_IRQ
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config GRACKLE_PCI
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select PCI
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bool
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config UNIN_PCI
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bool
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select PCI
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select DEC_PCI
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select OPENPIC
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config PPCE500_PCI
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select PCI
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bool
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config VERSATILE_PCI
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select PCI
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bool
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config PCI_SABRE
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select PCI
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bool
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config PCI_I440FX
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bool
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select PCI
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select PAM
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config PCI_EXPRESS_ASPEED
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bool
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select PCI_EXPRESS
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config PCI_EXPRESS_Q35
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bool
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select PCI_EXPRESS
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select PAM
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config PCI_EXPRESS_GENERIC_BRIDGE
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bool
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select PCI_EXPRESS
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imply ACPI_PCI
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config PCI_EXPRESS_XILINX
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bool
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select PCI_EXPRESS
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config PCI_EXPRESS_DESIGNWARE
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bool
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select PCI_EXPRESS
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select MSI_NONBROKEN
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config PCI_BONITO
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select PCI
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select UNIMP
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bool
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config PCI_POWERNV
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select PCI_EXPRESS
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select MSI_NONBROKEN
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select PCIE_PORT
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config REMOTE_PCIHOST
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bool
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config SH_PCI
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bool
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select PCI
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config ARTICIA
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bool
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select PCI
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select I8259
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config MV64361
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bool
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select PCI
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select I8259
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config DINO
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bool
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select PCI
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config ASTRO
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bool
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select PCI
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config PCI_EXPRESS_FSL_IMX8M_PHY
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bool
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config GT64120
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bool
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select PCI
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select EMPTY_SLOT
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select I8259
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