cbf0e6e3dc
We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for OpenRISC targets. We treat anything other than resets, timer and device interrupts as exceptions. Signed-off-by: Julian Ganz <neither@nut.email> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20251027110344.2289945-21-alex.bennee@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
136 lines
4.1 KiB
C
136 lines
4.1 KiB
C
/*
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* OpenRISC interrupt.
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "gdbstub/helpers.h"
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#include "qemu/host-utils.h"
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#ifndef CONFIG_USER_ONLY
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#include "hw/loader.h"
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#endif
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#include "qemu/plugin.h"
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void openrisc_cpu_do_interrupt(CPUState *cs)
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{
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CPUOpenRISCState *env = cpu_env(cs);
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int exception = cs->exception_index;
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uint64_t last_pc = env->pc;
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env->epcr = env->pc;
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/* When we have an illegal instruction the error effective address
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shall be set to the illegal instruction address. */
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if (exception == EXCP_ILLEGAL) {
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env->eear = env->pc;
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}
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/* During exceptions esr is populared with the pre-exception sr. */
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env->esr = cpu_get_sr(env);
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/* In parallel sr is updated to disable mmu, interrupts, timers and
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set the delay slot exception flag. */
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env->sr &= ~SR_DME;
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env->sr &= ~SR_IME;
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env->sr |= SR_SM;
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env->sr &= ~SR_IEE;
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env->sr &= ~SR_TEE;
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env->pmr &= ~PMR_DME;
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env->pmr &= ~PMR_SME;
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env->lock_addr = -1;
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/* Set/clear dsx to indicate if we are in a delay slot exception. */
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if (env->dflag) {
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env->dflag = 0;
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env->sr |= SR_DSX;
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env->epcr -= 4;
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} else {
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env->sr &= ~SR_DSX;
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if (exception == EXCP_SYSCALL || exception == EXCP_FPE) {
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env->epcr += 4;
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}
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}
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if (exception > 0 && exception < EXCP_NR) {
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static const char * const int_name[EXCP_NR] = {
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[EXCP_RESET] = "RESET",
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[EXCP_BUSERR] = "BUSERR (bus error)",
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[EXCP_DPF] = "DFP (data protection fault)",
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[EXCP_IPF] = "IPF (code protection fault)",
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[EXCP_TICK] = "TICK (timer interrupt)",
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[EXCP_ALIGN] = "ALIGN",
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[EXCP_ILLEGAL] = "ILLEGAL",
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[EXCP_INT] = "INT (device interrupt)",
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[EXCP_DTLBMISS] = "DTLBMISS (data tlb miss)",
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[EXCP_ITLBMISS] = "ITLBMISS (code tlb miss)",
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[EXCP_RANGE] = "RANGE",
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[EXCP_SYSCALL] = "SYSCALL",
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[EXCP_FPE] = "FPE",
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[EXCP_TRAP] = "TRAP",
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};
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qemu_log_mask(CPU_LOG_INT, "CPU: %d INT: %s\n",
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cs->cpu_index,
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int_name[exception]);
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hwaddr vect_pc = exception << 8;
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if (env->cpucfgr & CPUCFGR_EVBARP) {
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vect_pc |= env->evbar;
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}
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if (env->sr & SR_EPH) {
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vect_pc |= 0xf0000000;
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}
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env->pc = vect_pc;
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} else {
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cpu_abort(cs, "Unhandled exception 0x%x\n", exception);
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}
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switch (exception) {
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case EXCP_RESET:
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/* Resets are already exposed to plugins through a dedicated callback */
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break;
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case EXCP_TICK:
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case EXCP_INT:
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qemu_plugin_vcpu_interrupt_cb(cs, last_pc);
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break;
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default:
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qemu_plugin_vcpu_exception_cb(cs, last_pc);
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break;
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}
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cs->exception_index = -1;
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}
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bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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CPUOpenRISCState *env = cpu_env(cs);
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int idx = -1;
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if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) {
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idx = EXCP_INT;
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}
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if ((interrupt_request & CPU_INTERRUPT_TIMER) && (env->sr & SR_TEE)) {
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idx = EXCP_TICK;
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}
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if (idx >= 0) {
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cs->exception_index = idx;
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openrisc_cpu_do_interrupt(cs);
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return true;
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}
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return false;
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}
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