227 lines
6.4 KiB
C
227 lines
6.4 KiB
C
#include "qemu/osdep.h"
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#include "exec/cputlb.h"
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#include "accel/tcg/cpu-ops.h"
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#include "hw/resettable.h"
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#include "qemu/qemu-print.h"
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#include "qemu/typedefs.h"
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#include "qom/object.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "disas/dis-asm.h"
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#include "exec/cpu-interrupt.h"
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#include "exec/target_page.h"
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static void cr16c_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) {
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info->mach = bfd_arch_cr16c;
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info->endian = BFD_ENDIAN_LITTLE;
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info->print_insn = cr16c_print_insn;
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}
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static void cr16c_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState* cs = CPU(dev);
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CR16CCPUClass* ccc = CR16C_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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qemu_init_vcpu(cs);
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cpu_reset(cs);
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ccc->parent_realize(dev, errp);
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}
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static void cr16c_cpu_reset_hold(Object *obj, ResetType type)
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{
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CPUState *cs = CPU(obj);
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CR16CCPU *cpu = CR16C_CPU(cs);
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CR16CCPUClass *ccc = CR16C_CPU_GET_CLASS(obj);
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CPUCR16CState* env = &cpu->env;
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// TODO: Interrupts
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if (ccc->parent_phases.hold) {
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ccc->parent_phases.hold(obj, type);
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}
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for(int i = 0; i < CR16C_REG_COUNT; i++) {
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env->r[i] = 0;
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}
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env->r[0] = env->pc;
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env->r[1] = env->pc >> 16;
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env->psr_n = 0;
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env->psr_z = 0;
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env->psr_f = 0;
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env->psr_l = 0;
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env->psr_c = 0;
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env->psr_t = 0;
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env->psr_u = 0;
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env->psr_e = 0;
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env->psr_p = 0;
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env->psr_i = 0;
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env->pc = 0;
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}
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static ObjectClass* cr16c_cpu_class_by_name(const char *cpu_model) {
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return object_class_by_name(TYPE_CR16C_CPU);
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}
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static bool cr16c_cpu_has_work(CPUState *cs)
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{
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CR16CCPU *cpu = CR16C_CPU(cs);
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CPUCR16CState *env = &cpu->env;
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return (cs->interrupt_request & CPU_INTERRUPT_HARD) && cpu_interrupts_enabled(env);
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}
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static void cr16c_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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CPUCR16CState* env = cpu_env(cs);
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qemu_fprintf(f, "-- Special purpose registers --\n");
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qemu_fprintf(f, "PC: " TARGET_FMT_lx "\n", env->pc);
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qemu_fprintf(f, "-- General purpose registers --\n");
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for(int i = 0; i < 10; i++) {
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qemu_fprintf(f, "R%d: %04x\n", i, env->r[i]);
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}
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for(int i = 10; i < CR16C_FIRST_32B_REG; i++) {
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qemu_fprintf(f, "R%d: %04x\n", i, env->r[i]);
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}
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for(int i = CR16C_FIRST_32B_REG; i < CR16C_REG_COUNT - 2; i++) {
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qemu_fprintf(f, "R%d: %08x\n", i, env->r[i]);
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}
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qemu_fprintf(f, "RA: " TARGET_FMT_lx "\n", env->r[CR16C_REGNO_RA]);
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qemu_fprintf(f, "SP: " TARGET_FMT_lx "\n", env->r[CR16C_REGNO_SP]);
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qemu_fprintf(f, "-- Flags --\n");
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qemu_fprintf(f, "PSR: %04x\n", cr16c_cpu_pack_psr(env));
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qemu_fprintf(f, ". I P E N Z F U L T C\n");
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qemu_fprintf(f, ". %d %d %d %d %d %d %d %d %d %d\n",
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env->psr_i, env->psr_p, env->psr_e, env->psr_n, env->psr_z, env->psr_f, env->psr_u, env->psr_l, env->psr_t, env->psr_c);
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qemu_fprintf(f, "CFG: %04x\n", cr16c_cpu_pack_cfg(env));
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qemu_fprintf(f, ". SR ED LIC IC DC\n");
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qemu_fprintf(f, ". %d %d %d %d %d\n",
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env->cfg_sr, env->cfg_ed, env->cfg_lic, env->cfg_ic, env->cfg_dc);
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qemu_fprintf(f, "\n");
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}
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/* For debugging only, until tracing and exceptions are implemented */
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void cr16c_debug_dump_state(CPUState *cs) {
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cr16c_cpu_dump_state(cs, stdout, 0);
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}
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static void cr16c_cpu_set_pc(CPUState *cs, vaddr value)
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{
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CR16CCPU *cpu = CR16C_CPU(cs);
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cpu->env.pc = value;
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}
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static vaddr cr16c_cpu_get_pc(CPUState *cs)
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{
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CR16CCPU *cpu = CR16C_CPU(cs);
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return cpu->env.pc;
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}
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static int cr16c_cpu_mmu_index(CPUState *cs, bool ifetch)
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{
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return 0;
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}
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static bool cr16c_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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// TODO
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return false;
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}
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hwaddr cr16c_cpu_get_phys_page_debug(CPUState* cs, vaddr addr) {
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return addr;
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}
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static TCGTBCPUState cr16c_cpu_get_tb_cpu_state(CPUState *cs) {
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CPUCR16CState *env = cpu_env(cs);
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return (TCGTBCPUState){ .pc = env->pc };
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}
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bool cr16c_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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/* Copied from rx */
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uint32_t address, physical, prot;
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/* Linear mapping */
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address = physical = addr & TARGET_PAGE_MASK;
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
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return true;
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}
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void cr16c_restore_state_to_opc(CPUState *cpu, const TranslationBlock *tb,
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const uint64_t *data) {
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qemu_printf("idk what im doing!!!!!!\n");
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// TODO figure out what this is supposed to do and implement it
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}
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#include "hw/core/sysemu-cpu-ops.h"
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static const struct SysemuCPUOps cr16c_sysemu_ops = {
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.get_phys_page_debug = cr16c_cpu_get_phys_page_debug,
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.has_work = cr16c_cpu_has_work,
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};
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static const struct TCGCPUOps cr16c_tcg_ops = {
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.initialize = cr16c_translate_init,
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.mmu_index = cr16c_cpu_mmu_index,
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.cpu_exec_interrupt = cr16c_cpu_exec_interrupt,
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.cpu_exec_reset = cpu_reset,
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.translate_code = cr16c_translate_code,
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.get_tb_cpu_state = cr16c_cpu_get_tb_cpu_state,
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.restore_state_to_opc = cr16c_restore_state_to_opc,
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.tlb_fill = cr16c_cpu_tlb_fill,
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.pointer_wrap = cpu_pointer_wrap_notreached,
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.cpu_exec_halt = cr16c_cpu_has_work,
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};
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static void cr16c_cpu_class_init(ObjectClass *oc, const void *data)
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{
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CR16CCPUClass *acc = CR16C_CPU_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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ResettableClass *rc = RESETTABLE_CLASS(cc);
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device_class_set_parent_realize(dc, cr16c_cpu_realizefn, &acc->parent_realize);
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resettable_class_set_parent_phases(rc, NULL, cr16c_cpu_reset_hold, NULL, &acc->parent_phases);
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cc->class_by_name = cr16c_cpu_class_by_name;
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cc->dump_state = cr16c_cpu_dump_state;
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cc->set_pc = cr16c_cpu_set_pc;
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cc->get_pc = cr16c_cpu_get_pc;
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cc->sysemu_ops = &cr16c_sysemu_ops;
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cc->disas_set_info = cr16c_cpu_disas_set_info;
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cc->tcg_ops = &cr16c_tcg_ops;
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}
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static const TypeInfo cr16c_cpu_archs[] = {
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{
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.name = TYPE_CR16C_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(CR16CCPU),
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.class_size = sizeof(CR16CCPUClass),
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.class_init = cr16c_cpu_class_init,
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},
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};
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DEFINE_TYPES(cr16c_cpu_archs)
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