Richard Henderson 09cbd50198 target/arm: Convert jazelle from feature bit to isar1 test ... Having V6 alone imply jazelle was wrong for cortex-m0. Change to an assertion for V6 & !M. This was harmless, because the only place we tested ARM_FEATURE_JAZELLE was for 'bxj' in disas_arm(), which is unreachable for M-profile cores. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181016223115.24100-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2018-10-24 07:50:17 +01:00
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alpha	target/alpha: remove tlb_flush from alpha_cpu_initfn	2018-10-18 18:58:10 -07:00
arm	target/arm: Convert jazelle from feature bit to isar1 test	2018-10-24 07:50:17 +01:00
cris	target/cris/translate: Get rid of qemu_log_separate()	2018-10-16 17:57:23 +02:00
hppa	target/hppa: Raise exception 26 on emulated hardware	2018-10-16 15:32:22 -07:00
i386	Error reporting patches for 2018-10-22	2018-10-23 17:20:23 +01:00
lm32
m68k
microblaze
mips	target/mips: Add opcodes for nanoMIPS EVA instructions	2018-10-18 20:37:20 +02:00
moxie
nios2
openrisc	target/openrisc: Fix writes to interrupt mask register	2018-07-03 22:40:33 +09:00
ppc	Error reporting patches for 2018-10-22	2018-10-23 17:20:23 +01:00
riscv	riscv: remove define cpu_init()	2018-09-05 09:58:38 -07:00
s390x	target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translate	2018-10-18 19:46:53 -07:00
sh4	sh4: fix use_icount with linux-user	2018-08-20 00:11:06 +02:00
sparc	SPARC64: add icount support	2018-06-17 11:13:06 +01:00
tilegx
tricore
unicore32	target/unicore32: remove tlb_flush from uc32_init_fn	2018-10-18 18:58:10 -07:00
xtensa	target/xtensa: extract gen_check_interrupts call	2018-10-01 11:08:36 -07:00