fridtjof/qemu-cr16
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions
qemu-cr16/include/hw/riscv
History
Daniel Henrique Barboza 60c7dfa2a3 hw/riscv/sifive_u: use 'fdt' from MachineState 
The MachineState object provides a 'fdt' pointer that is already being
used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP
command.

Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt
instead.

Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20230102115241.25733-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-20 10:14:13 +10:00
..
boot.h hw/riscv/boot.c: Introduce riscv_find_firmware() 2023-01-20 10:14:13 +10:00
boot_opensbi.h include: Include headers where needed 2023-01-08 01:54:22 -05:00
microchip_pfsoc.h include: Include headers where needed 2023-01-08 01:54:22 -05:00
numa.h include: Include headers where needed 2023-01-08 01:54:22 -05:00
opentitan.h hw/riscv/opentitan: add aon_timer base unimpl 2023-01-06 10:42:55 +10:00
riscv_hart.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
shakti_c.h hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 2023-01-06 10:42:55 +10:00
sifive_cpu.h riscv: Add a sifive_cpu.h to include both E and U cpu type defines 2019-09-17 08:42:46 -07:00
sifive_e.h hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 2023-01-06 10:42:55 +10:00
sifive_u.h hw/riscv/sifive_u: use 'fdt' from MachineState 2023-01-20 10:14:13 +10:00
spike.h hw/riscv/spike: use 'fdt' from MachineState 2023-01-20 10:14:13 +10:00
virt.h include: Include headers where needed 2023-01-08 01:54:22 -05:00