qemu-cr16/target
Zhao Liu 25acae4c6e i386/cpu: Select legacy cache model based on vendor in CPUID 0x8000001D
As preparation for merging cache_info_cpuid4 and cache_info_amd in
X86CPUState, set legacy cache model based on vendor in the CPUID
0x8000001D leaf. For AMD CPU, select legacy AMD cache model (in
cache_info_amd) as the default cache model like before, otherwise,
select legacy Intel cache model (in cache_info_cpuid4).

In fact, for Intel (and Zhaoxin) CPU, this change is safe because the
extended CPUID level supported by Intel is up to 0x80000008. So Intel
Guest doesn't have this 0x8000001D leaf.

Although someone could bump "xlevel" up to 0x8000001D for Intel Guest,
it's meaningless and this is undefined behavior. This leaf should be
considered reserved, but the SDM does not explicitly state this. So,
there's no need to specifically use vendor_cpuid_only_v2 to fix
anything, as it doesn't even qualify as a fix since nothing is
currently broken.

Therefore, it is acceptable to select the default legacy cache model
based on the vendor.

For the CPUID 0x8000001D leaf, in X86CPUState, a unified cache_info is
enough. It only needs to be initialized and configured with the
corresponding legacy cache model based on the vendor.

Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250711102143.1622339-18-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-07-12 15:28:22 +02:00
..
alpha target: Use cpu_pointer_wrap_notreached for strict align targets 2025-05-28 08:08:47 +01:00
arm target-arm queue: 2025-07-07 09:22:41 -04:00
avr target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
hexagon accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 2025-04-30 12:45:05 -07:00
hppa target: Use cpu_pointer_wrap_notreached for strict align targets 2025-05-28 08:08:47 +01:00
i386 i386/cpu: Select legacy cache model based on vendor in CPUID 0x8000001D 2025-07-12 15:28:22 +02:00
loongarch treewide: fix paths for relocated files in comments 2025-07-02 18:26:27 +02:00
m68k target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
microblaze target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
mips * target/i386/kvm: Intel TDX support 2025-05-30 11:41:07 -04:00
openrisc target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
ppc * target/i386/kvm: Intel TDX support 2025-05-30 11:41:07 -04:00
riscv target: riscv: Add Svrsw60t59b extension support 2025-07-04 21:09:49 +10:00
rx target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
s390x target/s390x: A fix for the trouble with tribles 2025-07-02 18:29:57 +02:00
sh4 target: Use cpu_pointer_wrap_notreached for strict align targets 2025-05-28 08:08:47 +01:00
sparc accel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOW 2025-05-28 15:17:25 -04:00
tricore target: Use cpu_pointer_wrap_uint32 for 32-bit targets 2025-05-28 08:08:48 +01:00
xtensa target/xtensa: replace FSF postal address with licenses URL 2025-06-26 00:42:37 +02:00
Kconfig
meson.build