qemu-cr16/hw/riscv
Li Chen 54401d5abd acpi: Add machine option to disable SPCR table
The ACPI SPCR (Serial Port Console Redirection) table allows firmware
to specify a preferred serial console device to the operating system.
On ARM64 systems, Linux by default respects this table: even if the
kernel command line does not include a hardware serial console (e.g.,
"console=ttyAMA0"), the kernel still register the serial device
referenced by SPCR as a printk console.

While this behavior is standard-compliant, it can lead to situations
where guest console behavior is influenced by platform firmware rather
than user-specified configuration. To make guest console behavior more
predictable and under user control, this patch introduces a machine
option to explicitly disable SPCR table exposure:

    -machine spcr=off

By default, the option is enabled (spcr=on), preserving existing
behavior. When disabled, QEMU will omit the SPCR table from the guest's
ACPI namespace, ensuring that only consoles explicitly declared in the
kernel command line are registered.

Signed-off-by: Li Chen <chenl311@chinatelecom.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Message-Id: <20250528105404.457729-2-me@linux.beauty>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-07-14 09:16:40 -04:00
..
boot.c target/riscv: store RISCVCPUDef struct directly in the class 2025-05-20 08:18:53 +02:00
Kconfig hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype 2025-07-04 21:09:49 +10:00
meson.build hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype 2025-07-04 21:09:49 +10:00
microblaze-v-generic.c include/system: Move exec/address-spaces.h to system/address-spaces.h 2025-04-23 14:08:21 -07:00
microchip_pfsoc.c hw/riscv: Configurable MPFS CLINT timebase freq 2025-05-19 13:30:24 +10:00
numa.c include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
opentitan.c qom: Have class_init() take a const data argument 2025-04-25 17:00:41 +02:00
riscv-iommu-bits.h target: riscv: Add Svrsw60t59b extension support 2025-07-04 21:09:49 +10:00
riscv-iommu-hpm.c hw/riscv: add IOMMU HPM trace events 2025-03-04 15:42:54 +10:00
riscv-iommu-hpm.h hw/riscv/riscv-iommu: add hpm events mmio write 2025-03-04 15:42:54 +10:00
riscv-iommu-pci.c hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class 2025-06-10 12:59:09 +02:00
riscv-iommu-sys.c hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class 2025-06-10 12:59:09 +02:00
riscv-iommu.c target: riscv: Add Svrsw60t59b extension support 2025-07-04 21:09:49 +10:00
riscv-iommu.h hw/riscv/riscv-iommu: add hpm events mmio write 2025-03-04 15:42:54 +10:00
riscv_hart.c target/riscv: Pass ra to riscv_csrrw 2025-05-19 13:39:29 +10:00
shakti_c.c qom: Have class_init() take a const data argument 2025-04-25 17:00:41 +02:00
sifive_e.c qom: Have class_init() take a const data argument 2025-04-25 17:00:41 +02:00
sifive_u.c qom: Have class_init() take a const data argument 2025-04-25 17:00:41 +02:00
spike.c qom: Have class_init() take a const data argument 2025-04-25 17:00:41 +02:00
trace-events hw/riscv: add IOMMU HPM trace events 2025-03-04 15:42:54 +10:00
trace.h hw/riscv: add RISC-V IOMMU base emulation 2024-10-31 13:51:24 +10:00
virt-acpi-build.c acpi: Add machine option to disable SPCR table 2025-07-14 09:16:40 -04:00
virt.c hw/riscv/virt: Use setprop_sized_cells for pcie 2025-07-04 21:09:49 +10:00
xiangshan_kmh.c hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype 2025-07-04 21:09:49 +10:00