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qemu-cr16/target/arm/tcg
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Peter Maydell 7428c46c06 target/arm: Fix LD1W, LD1D to 128-bit elements 
In our implementation of the SVE2p1 contiguous load to 128-bit
element insns such as LD1D (scalar plus scalar, single register), we
got the order of the arguments to the DO_LD1_2() macro wrong.  Here
the first argument is the element size and the second is the memory
size, and the element size is always the same size or larger than
the memory size.

For the 128-bit versions, we want to load either 32-bit or 64-bit
values from memory and extend them to the 128-bit vector element, but
were trying to load 128 bit values and then stuff them into 32-bit or
64-bit vector elements.  Correct the macro ordering.

Fixes: fc5f060bcb ("target/arm: Implement {LD1, ST1}{W, D} (128-bit element) for SVE2p1")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250723165458.3509150-7-peter.maydell@linaro.org
2025-07-25 10:31:45 +01:00
..
a32-uncond.decode
a32.decode
a64.decode target/arm: Add decodetree entry for DSB nXS variant 2024-12-17 15:17:46 +00:00
arith_helper.c target/arm/tcg/arith_helper: compile file once 2025-05-14 15:12:40 +01:00
arm_ldst.h target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/ 2023-05-12 15:43:36 +01:00
cpregs-at.c target/arm: Split out AT insns to tcg/cpregs-at.c 2025-07-10 09:16:46 +01:00
cpu-v7m.c arm/cpu: store clidr into the idregs array 2025-07-10 09:13:03 +01:00
cpu32.c arm/cpu: store clidr into the idregs array 2025-07-10 09:13:03 +01:00
cpu64.c arm/cpu: store clidr into the idregs array 2025-07-10 09:13:03 +01:00
crypto_helper.c target/arm/tcg/crypto_helper: compile file once 2025-05-14 15:12:40 +01:00
gengvec.c target/arm: Introduce gen_gvec_urecpe, gen_gvec_ursqrte 2024-12-13 13:39:24 +00:00
gengvec64.c target/arm: Introduce gen_gvec_sve2_sqdmulh 2025-07-04 15:52:21 +01:00
helper-a64.c target/arm: Don't enforce NSE,NS check for EL3->EL3 returns 2025-07-10 09:23:24 +01:00
helper-a64.h target/arm: Handle FPCR.AH in FRECPS and FRSQRTS scalar insns 2025-02-11 16:22:07 +00:00
helper-mve.h target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/ 2023-05-12 15:43:37 +01:00
helper-sme.h target/arm: Expand the descriptor for SME/SVE memory ops to i64 2025-07-25 10:31:45 +01:00
helper-sve.h target/arm: Expand the descriptor for SME/SVE memory ops to i64 2025-07-25 10:31:45 +01:00
helper.h target/arm: Add BFMUL (indexed) 2025-07-21 11:13:55 +01:00
hflags.c target/arm: Add zt0_excp_el to DisasContext 2025-07-04 15:52:21 +01:00
iwmmxt_helper.c target/arm/tcg/iwmmxt_helper: compile file twice (system, user) 2025-05-14 15:12:40 +01:00
m-nocp.decode
m_helper.c target/arm: Fix function_return helper load alignment checks 2025-07-04 13:44:20 +01:00
meson.build target/arm: Split out AT insns to tcg/cpregs-at.c 2025-07-10 09:16:46 +01:00
mte_helper.c accel/tcg: Remove TARGET_PAGE_DATA_SIZE 2025-05-05 09:24:10 -07:00
mte_helper.h target/arm: Make some MTE helpers widely available 2024-07-05 12:35:11 +01:00
mve.decode
mve_helper.c target/arm: Move do_urshr, do_srshr to vec_internal.h 2025-07-04 15:52:22 +01:00
neon-dp.decode target/arm: Convert VQSHL, VQSHLU to gvec 2024-09-19 12:58:58 +01:00
neon-ls.decode
neon-shared.decode
neon_helper.c target/arm: Implement SME2 Multiple and Single SVE Destructive 2025-07-04 15:52:21 +01:00
op_addsub.c.inc target/arm: Move minor arithmetic helpers out of helper.c 2025-01-13 12:35:34 +00:00
op_helper.c target/arm/helper: use vaddr instead of target_ulong for probe_access 2025-05-14 15:12:40 +01:00
pauth_helper.c include: Remove 'exec/exec-all.h' 2025-04-30 12:45:05 -07:00
psci.c include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
sme-fa64.decode
sme.decode target/arm: Implement SME2 BFMOPA (non-widening) 2025-07-04 15:53:23 +01:00
sme_helper.c target/arm: Pack mtedesc into upper 32 bits of descriptor 2025-07-25 10:31:45 +01:00
sve.decode target/arm: LD1Q, ST1Q are vector + scalar, not scalar + vector 2025-07-25 10:31:45 +01:00
sve_helper.c target/arm: Fix LD1W, LD1D to 128-bit elements 2025-07-25 10:31:45 +01:00
sve_ldst_internal.h target/arm: Move ld1qq and st1qq primitives to sve_ldst_internal.h 2025-07-04 15:53:23 +01:00
t16.decode
t32.decode target/arm: Use PLD, PLDW, PLI not NOP for t32 2024-05-28 14:23:52 +01:00
tlb-insns.c target/arm/tcg/tlb-insns: compile file once (system) 2025-05-14 15:12:40 +01:00
tlb_helper.c target/arm/tcg/tlb_helper: compile file twice (system, user) 2025-05-14 15:12:40 +01:00
translate-a32.h target/arm: Implement store_cpu_field_low32() macro 2024-07-11 11:41:33 +01:00
translate-a64.c target/arm: Rename helper_gvec_*dot_[bh] to *_4[bh] 2025-07-04 15:52:22 +01:00
translate-a64.h target/arm: Expand the descriptor for SME/SVE memory ops to i64 2025-07-25 10:31:45 +01:00
translate-m-nocp.c target/arm: Rename FPCR_ QC, NZCV macros to FPSR_ 2024-07-11 11:41:33 +01:00
translate-mve.c tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
translate-neon.c target/arm: Rename gvec_fml[as]_[hs] with _nf_ infix 2025-07-04 15:52:22 +01:00
translate-sme.c target/arm: Expand the descriptor for SME/SVE memory ops to i64 2025-07-25 10:31:45 +01:00
translate-sve.c target/arm: LD1Q, ST1Q are vector + scalar, not scalar + vector 2025-07-25 10:31:45 +01:00
translate-vfp.c target/arm: Use FPST_A32_F16 in A32 decoder 2025-01-28 18:40:19 +00:00
translate.c target/arm: Unify gen_exception_internal() 2025-07-01 15:08:32 +01:00
translate.h target/arm: Implement SME2 ADD/SUB (array results, multiple and single vector) 2025-07-04 15:52:21 +01:00
vec_helper.c target/arm: Add BFMUL (indexed) 2025-07-21 11:13:55 +01:00
vec_internal.h target/arm: Support FPCR.AH in SME FMOPS, BFMOPS 2025-07-04 15:53:23 +01:00
vfp-uncond.decode
vfp.decode target/arm: Correct names of VFP VFNMA and VFNMS insns 2024-09-05 13:12:37 +01:00
vfp_helper.c target/arm: Introduce FPST_ZA, FPST_ZA_F16 2025-07-04 15:52:21 +01:00