256df51e72
This patch replaces the obsolete IOCSR_BRD bit with CRC in cpucfg1[25], in both LA464 and LA132 CPU initialization functions. The corresponding field macro in `cpu.h` is updated to reflect this change. Additionally, the availability macro `avail_CRC()` is introduced in `translate.h` to check the CRC feature flag. All CRC-related instruction translations are updated to be gated by the new CRC feature flag instead of hardcoded CPU features. This ensures correctness and configurability when enabling CRC instructions based on hardware capabilities. Signed-off-by: WANG Rui <wangrui@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250418082103.447780-2-wangrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
61 lines
1.9 KiB
C
61 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* LoongArch translation routines.
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*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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#ifndef TARGET_LOONGARCH_TRANSLATE_H
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#define TARGET_LOONGARCH_TRANSLATE_H
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#include "exec/translator.h"
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#define TRANS(NAME, AVAIL, FUNC, ...) \
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static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
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{ return avail_##AVAIL(ctx) && FUNC(ctx, a, __VA_ARGS__); }
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#define avail_ALL(C) true
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#define avail_64(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, ARCH) == \
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CPUCFG1_ARCH_LA64)
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#define avail_FP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP))
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#define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP))
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#define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP))
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#define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW))
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#define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM))
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#define avail_LSX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX))
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#define avail_LASX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LASX))
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#define avail_IOCSR(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, IOCSR))
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#define avail_CRC(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, CRC))
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/*
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* If an operation is being performed on less than TARGET_LONG_BITS,
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* it may require the inputs to be sign- or zero-extended; which will
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* depend on the exact operation being performed.
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*/
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typedef enum {
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EXT_NONE,
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EXT_SIGN,
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EXT_ZERO,
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} DisasExtend;
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typedef struct DisasContext {
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DisasContextBase base;
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target_ulong page_start;
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uint32_t opcode;
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uint16_t mem_idx;
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uint16_t plv;
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int vl; /* Vector length */
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TCGv zero;
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bool la64; /* LoongArch64 mode */
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bool va32; /* 32-bit virtual address */
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uint32_t cpucfg1;
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uint32_t cpucfg2;
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} DisasContext;
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void generate_exception(DisasContext *ctx, int excp);
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extern TCGv cpu_gpr[32], cpu_pc;
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extern TCGv_i32 cpu_fscr0;
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extern TCGv_i64 cpu_fpr[32];
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#endif
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