65a67f0fe5
Having the callee add 1 to shift amount is misleading (see the NM_LSA case in decode_nanomips_32_48_opc() where we have to manually substract 1). Rather have the callers pass a modified $sa. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241112172022.88348-4-philmd@linaro.org>
47 lines
1.1 KiB
C
47 lines
1.1 KiB
C
/*
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* MIPS emulation for QEMU - Release 6 translation routines
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*
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* Copyright (c) 2020 Philippe Mathieu-Daudé
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*
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* This code is licensed under the LGPL v2.1 or later.
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*/
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#include "qemu/osdep.h"
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#include "translate.h"
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/* Include the auto-generated decoders. */
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#include "decode-rel6.c.inc"
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bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a)
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{
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gen_reserved_instruction(ctx);
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return true;
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}
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static bool trans_LSA(DisasContext *ctx, arg_r *a)
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{
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return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
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}
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static bool trans_DLSA(DisasContext *ctx, arg_r *a)
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{
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if (TARGET_LONG_BITS != 64) {
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return false;
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}
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return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);
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}
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static bool trans_CRC32(DisasContext *ctx, arg_special3_crc *a)
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{
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if (unlikely(!ctx->crcp)
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|| unlikely((a->sz == 3) && (!(ctx->hflags & MIPS_HFLAG_64)))
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|| unlikely((a->c >= 2))) {
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gen_reserved_instruction(ctx);
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return true;
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}
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gen_crc32(ctx, a->rt, a->rs, a->rt, a->sz, a->c);
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return true;
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}
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