qemu-cr16/target/riscv/insn_trans
Daniel Henrique Barboza 09ac27a9b5 riscv: Revert "Generate strided vector loads/stores with tcg nodes."
This reverts commit 28c12c1f2f.

As reported in [1] this commit is breaking Linux vector code, and
although a simpler reproducer was provided, the fix itself isn't trivial
due to the amount and the nature of the changes. And we really do not
want to keep Linux broken while we work on it.

The revert will fix Linux and will give us time to do a proper fix.

[1] https://mail.gnu.org/archive/html/qemu-devel/2025-07/msg02525.html

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Tested-by: Eric Biggers <ebiggers@kernel.org>
Message-ID: <20250710100525.372985-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-07-30 10:59:26 +10:00
..
trans_privileged.c.inc target/riscv: Add CTR sctrclr instruction. 2025-03-04 15:42:54 +10:00
trans_rva.c.inc target/riscv: update decode_save_opc to store extra word2 2024-10-30 11:22:08 +10:00
trans_rvb.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvbf16.c.inc target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen instructions 2025-05-19 13:39:10 +10:00
trans_rvd.c.inc target/riscv: update decode_save_opc to store extra word2 2024-10-30 11:22:08 +10:00
trans_rvf.c.inc target/riscv: update decode_save_opc to store extra word2 2024-10-30 11:22:08 +10:00
trans_rvh.c.inc target/riscv: update decode_save_opc to store extra word2 2024-10-30 11:22:08 +10:00
trans_rvi.c.inc target/riscv: Add check for 16-bit aligned PC for different priv versions. 2025-03-19 17:11:46 +10:00
trans_rvk.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvm.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvv.c.inc riscv: Revert "Generate strided vector loads/stores with tcg nodes." 2025-07-30 10:59:26 +10:00
trans_rvvk.c.inc target/riscv: update decode_save_opc to store extra word2 2024-10-30 11:22:08 +10:00
trans_rvzabha.c.inc target/riscv: Add amocas.[b|h] for Zabha 2024-07-18 12:00:42 +10:00
trans_rvzacas.c.inc target/riscv: update decode_save_opc to store extra word2 2024-10-30 11:22:08 +10:00
trans_rvzawrs.c.inc target/riscv: Raise exceptions on wrs.nto 2024-06-03 11:12:11 +10:00
trans_rvzce.c.inc target/riscv: Add support to record CTR entries. 2025-03-04 15:42:54 +10:00
trans_rvzcmop.c.inc target/riscv: Add zcmop extension 2024-07-18 12:00:42 +10:00
trans_rvzfa.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvzfh.c.inc target/riscv: update decode_save_opc to store extra word2 2024-10-30 11:22:08 +10:00
trans_rvzicbo.c.inc target/riscv: rvzicbo: Fixup CBO extension register calculation 2024-06-03 11:12:12 +10:00
trans_rvzicfiss.c.inc target/riscv: fixes a bug against ssamoswap behavior in M-mode 2025-03-19 16:34:32 +10:00
trans_rvzicond.c.inc target/riscv: refactor Zicond support 2023-05-05 10:49:50 +10:00
trans_rvzimop.c.inc target/riscv: Add zimop extension 2024-07-18 12:00:42 +10:00
trans_svinval.c.inc target/riscv: update decode_save_opc to store extra word2 2024-10-30 11:22:08 +10:00
trans_xthead.c.inc target/riscv: Enable xtheadsync under user mode 2024-02-09 20:43:14 +10:00
trans_xventanacondops.c.inc target/riscv: redirect XVentanaCondOps to use the Zicond functions 2023-05-05 10:49:50 +10:00