c083f1f3de
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com> Reviewed-by: Aleksandar Rikalo <arikalo@gmail.com> Message-ID: <20250214173702.2308488-3-aleksandar.rakic@htecgroup.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
115 lines
5.2 KiB
C
115 lines
5.2 KiB
C
/*
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* Header file for wrappers around MIPS64R6 instructions assembler
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* invocations
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*
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* Copyright (C) 2019 Wave Computing, Inc.
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* Copyright (C) 2019 Aleksandar Markovic <amarkovic@wavecomp.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <https://www.gnu.org/licenses/>.
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*
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*/
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#ifndef WRAPPERS_MIPS64R6_H
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#define WRAPPERS_MIPS64R6_H
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#include <string.h>
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#define DO_MIPS64R6__RD__RS(suffix, mnemonic) \
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static inline void do_mips64r6_##suffix(const void *input, \
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void *output) \
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{ \
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__asm__ volatile ( \
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"ld $t1, 0(%0)\n\t" \
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#mnemonic " $t0, $t1\n\t" \
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"sd $t0, 0(%1)\n\t" \
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: \
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: "r" (input), "r" (output) \
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: "t0", "t1", "memory" \
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); \
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}
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DO_MIPS64R6__RD__RS(CLO, clo)
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DO_MIPS64R6__RD__RS(CLZ, clz)
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DO_MIPS64R6__RD__RS(DCLO, dclo)
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DO_MIPS64R6__RD__RS(DCLZ, dclz)
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DO_MIPS64R6__RD__RS(BITSWAP, bitswap)
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DO_MIPS64R6__RD__RS(DBITSWAP, dbitswap)
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#define DO_MIPS64R6__RD__RS_RT(suffix, mnemonic) \
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static inline void do_mips64r6_##suffix(const void *input1, \
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const void *input2, \
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void *output) \
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{ \
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__asm__ volatile ( \
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"ld $t1, 0(%0)\n\t" \
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"ld $t2, 0(%1)\n\t" \
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#mnemonic " $t0, $t1, $t2\n\t" \
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"sd $t0, 0(%2)\n\t" \
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: \
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: "r" (input1), "r" (input2), "r" (output) \
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: "t0", "t1", "memory" \
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); \
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}
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DO_MIPS64R6__RD__RS_RT(SLLV, sllv)
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DO_MIPS64R6__RD__RS_RT(SRLV, srlv)
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DO_MIPS64R6__RD__RS_RT(SRAV, srav)
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DO_MIPS64R6__RD__RS_RT(DSLLV, dsllv)
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DO_MIPS64R6__RD__RS_RT(DSRLV, dsrlv)
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DO_MIPS64R6__RD__RS_RT(DSRAV, dsrav)
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DO_MIPS64R6__RD__RS_RT(MUL, mul)
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DO_MIPS64R6__RD__RS_RT(MUH, muh)
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DO_MIPS64R6__RD__RS_RT(MULU, mulu)
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DO_MIPS64R6__RD__RS_RT(MUHU, muhu)
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DO_MIPS64R6__RD__RS_RT(DMUL, dmul)
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DO_MIPS64R6__RD__RS_RT(DMUH, dmuh)
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DO_MIPS64R6__RD__RS_RT(DMULU, dmulu)
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DO_MIPS64R6__RD__RS_RT(DMUHU, dmuhu)
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#define DO_MIPS64R6__RT__RS_RT(suffix, mnemonic) \
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static inline void do_mips64r6_##suffix(const void *input1, \
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const void *input2, \
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void *output) \
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{ \
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if (strncmp(#mnemonic, "crc32", 5) == 0) \
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__asm__ volatile ( \
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".set crc\n\t" \
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); \
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\
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__asm__ volatile ( \
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"ld $t1, 0(%0)\n\t" \
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"ld $t2, 0(%1)\n\t" \
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#mnemonic " $t2, $t1, $t2\n\t" \
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"sd $t2, 0(%2)\n\t" \
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: \
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: "r" (input1), "r" (input2), "r" (output) \
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: "t0", "t1", "t2", "memory" \
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); \
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}
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DO_MIPS64R6__RT__RS_RT(CRC32B, crc32b)
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DO_MIPS64R6__RT__RS_RT(CRC32H, crc32h)
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DO_MIPS64R6__RT__RS_RT(CRC32W, crc32w)
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DO_MIPS64R6__RT__RS_RT(CRC32D, crc32d)
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DO_MIPS64R6__RT__RS_RT(CRC32CB, crc32cb)
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DO_MIPS64R6__RT__RS_RT(CRC32CH, crc32ch)
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DO_MIPS64R6__RT__RS_RT(CRC32CW, crc32cw)
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DO_MIPS64R6__RT__RS_RT(CRC32CD, crc32cd)
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#endif
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